2.2.1 Tradeoff Between Speed and Power Efficiency

Figure 2.1 illustrates the relations between the characteristic voltages and the figures of merit. These are shown for the possible ranges of and qualitatively in Table 2.1 and in Fig. 2.2. The noise immunity (often referred to as noise margins) is a key criterion to determine if the circuit works properly (cf. Section A.2.2.1). The obvious tradeoff between speed and power efficiency marks the useful range for the threshold voltage $0 < \ensuremath{V_{\mathit{T}}}\xspace < \ensuremath{V_{\mathit{DD}}}\xspace$.

Figure 2.1: Qualitative relations between supply and threshold voltage and speed and power efficiency

Table 2.1: Impact of threshold voltage on speed, power efficiency, and noise immunity

	power eff.	speed	noise margins
$>\ensuremath{V_{\mathit{DD}}}\xspace$	good	bad	good
$\approx\ensuremath{V_{\mathit{DD}}}\xspace$	good	poor	good	(mod. inversion determines speed)
$0 < \ensuremath{V_{\mathit{T}}}\xspace < \ensuremath{V_{\mathit{DD}}}\xspace$	fair	fair	fair
$\approx 0$	poor	good	poor	(mod. inversion determines power eff.)
<0	bad	good	bad

Most notably, the loci of optimum power efficiency (at acceptable speed) and for optimum speed are in the vicinity of $\ensuremath{V_{\mathit{T}}}\xspace =\ensuremath{V_{\mathit{DD}}}\xspace$ and $\ensuremath{V_{\mathit{T}}}\xspace =0$. The condition $\ensuremath{V_{\mathit{GS}}}\xspace \approx\ensuremath{V_{\mathit{T}}}\xspace$, which marks the moderate-inversion region of a MOSFET (cf. Section A.1.2.3), is critical for the speed in the first case and critical for the power consumption and noise immunity in the second case. Unfortunately, this transition between weak and strong inversion is where many analytical device models lose their accuracy and so do numerical ULP analyses based on these models. Yet, such analyses are quite useful to obtain an overview over voltage ranges and rough values of and with a minimum numerical effort. The results of one such study of devices with $\ensuremath{L}\xspace = \rm0.13\mu m$ are shown in Fig. 2.3. Clock frequency and switching energy were computed according to (2.4), (2.5), and (2.6) respectively. The drain currents were computed with equations similar to the EKV model (cf. (4.6)). The choice of the device parameters was motivated by the projections for the year 2004 in the SIA roadmap of 1994 [3]. What the results indicate is that the switching energy can be significantly reduced by decreasing the supply voltage from 1.5V to 0.5V without compromising performance.

Figure 2.2: Impact of supply and threshold voltage on speed and power efficiency

Figure 2.3: Performance estimation of a $\rm0.13\mu m$ CMOS technology using an analytical device model: the area around $\ensuremath{V_{\mathit{DD}}}\xspace =\rm1.5V$ marks the conventional strategy, at $\ensuremath{V_{\mathit{DD}}}\xspace =\rm0.3V$ the optimum energy efficiency is reached, and area around $\ensuremath{V_{\mathit{DD}}}\xspace =\rm0.5V$ indicates good energy efficiency and speed.