Since the development of the planar process, the integration paradigm is to increase the number of devices on the wafer surface. However, one can clearly see that there is plenty of available space along the depth of the wafer. What prevented its utilization was the lack of processing know-how to handle three-dimensional (3D) integration. Furthermore, there was no commercial reason to invest in vertical integration, since planar devices sufficed so far. However, in the last decade, the scenario has changed due to the limitations presented in Section 1.2, and the proper use of the third dimension provides an alternative to continue along the miniaturization path. Moreover, 3D integration promises additional benefits, such as increased bandwidth, reduced power consumption, improved performance, and multi-functionality .