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# 4. Drive Current Optimization

In digital circuits the On'' and Off'' states correspond to High'' and Low'' voltage states of internal circuit nodes. Therefore, any time a binary condition changes, the respective node switches its voltage from Low'' (0 V) to High'' ( ), or vice versa.

With every switching of a circuit node, a certain amount of charge must be transferred depending on the total capacitance connected to the node. This capacitance consists of intrinsic parts (inside the device, for example, gate capacitance) and extrinsic parts (peripherals, for example, interconnection capacitance). To charge or discharge a circuit node, a current flow (drive current) must exist transporting electrons from or to the node. The time required for one switching event strongly depends on the amount of drive current that can be achieved.

In CMOS digital circuits this drive current is defined as the drain current of a MOS transistor with gate and drain connected to the supply voltage , and source and bulk grounded. It is often referred to as on-state current'' or simply on-current'' .

The channel leakage current is defined as the drain current with drain connected to the supply voltage and gate, source, and bulk grounded. It is often referred to as off-state current'' or simply off-current'' . The definition of these two currents is shown in Fig. 4.1.

There is an inherent correlation between the drive and leakage currents which means that neither of them can be set completely independently from the other. This means if the drive current is increased by reducing the threshold voltage, the leakage current will usually become higher, too. There is an upper limit for the allowed leakage current of a given technology to limit the stand-by power consumption which must be quite small for low-power systems. Therefore, for the drive current optimizations performed in this work the leakage current will be kept below a certain limit while maximizing the drive current.

The drive and leakage currents depend on several properties, namely the device geometry and the used materials, the contact resistances, the supply voltage, the temperature, and the doping profile. But amongst all these the doping profile offers best means to optimize the driving capabilities since it determines the inner function'' of a MOS transistor, and is, therefore, the key to a better device performance. Besides that the remaining parameters are, in most cases, already fixed or their optima are well known but constrained for manufacturability reasons.

The minimum gate length and the gate oxide thickness, for example, are implicitly defined for a given technology generation (see Section 1.1). Therefore, the device geometry is more or less given by what process technology offers. The minimum gate length is mainly limited by the lithography performance. For the gate oxide thickness, yield and lifetime issues have to be considered in addition to manufacturability (see Section 2.5).

The materials used for a technology are, in most cases, also defined by the technology itself, for example, a silicon bulk process with dual-polysilicon gates or SOI. Different gate insulator materials can be accounted for by an effective gate oxide thickness depending on the insulator's dielectric constant.

New gate materials have been reported lately which have a different work function difference than polysilicon, and can, therefore, be used to set the threshold voltage by other means than the doping profile [2,24,30,70].

Besides that, contact design offers the chance to reduce parasitic series resistances, for example, using elevated source/drain structures or new salicidation methods [77]. A silicide layer made of TiSi or CoSi, for instance, provides a high-conductivity interface between metal and silicon. The silicide is formed in a chemical reaction between the involved metal and the silicon surface. Compared to conventional contact structures the silicide contact can be built with a self-aligned technique using source and drain spacers on both sides of the gate polysilicon to define the salicidation area, thus saving one mask step [73].

The supply voltage is scaled down with the device geometry and fixed for a given technology. For ultra low-power applications the supply voltage scaling is usually more aggressive than for other technologies where issues like compatibility with former process generations are more important than, for instance, the availability of certain battery cell voltages for portable systems.

Next: 4.1 Target and Constraint Up: Michael Stockinger's Dissertation Previous: 3.2.3 Optimization Performance
Michael Stockinger
2000-01-05