3.7.1 Trench Isolation



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3.7.1 Trench Isolation

 

Trench isolation is a common technique for lateral separation of the n-channel transistor's p-tub (also called p-well) from the p-channel transistor's n-tub in a CMOS twin-tub process and therefore to isolate the two different types of transistors [Hil88b], or for isolating the bipolar transistor from the MOS-transistor in BiCMOS technology [Liu92].

In the example to be discussed, a layer of was deposited and used as an etch mask during reactive ion etching of silicon. The etch process was simulated performing a SAMPLE [Add91] anisotropic plasma assisted etch and a subsequent isotropic etch step. After trench formation we implanted boron with an energy of . For the simulation of the implantation step we used the analytical ion implantation module of PROMIS as described in Chapter 2. The trench geometry and the implanted boron profile are shown in Figure 3.7-1.

Then, a sidewall oxide is grown to form an insulating layer, the trench is filled with polysilicon, an oxide is grown to cap the trench and finally the is removed. Thereafter the standard CMOS process is proceeded. The total thermal budget of the process steps after implantation is approximated by at plus at . We simulated the effect of the thermal treatment using the diffusion model DIFN, neglecting the growth of the oxide. The final boron profile at the trench's bottom region is shown in Figure 3.7-2.

Since only boron but no other dopants are present in the bottom area of the trench (the adjacent n-well does not extend beyond 3 to 4 microns depth) the application of the uncoupled model DIFN is sufficient. Note, that the diffusion front is almost parallel to the grid lines of the curvilinear grid. This means that grid refinement by inserting grid lines parallel to the trench's inner surface is particularly efficient.

  



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Next: 3.7.2 LDD P-Channel Transistor Up: 3.7 Applications Previous: 3.7 Applications



Martin Stiftinger
Wed Oct 19 13:03:34 MET 1994