4. Electromigration Problem in the Interconnect

Electromigration is the main realibility issue in modern integrated circuits, which can trigger system failure at some undefined future time. The phenomenon is particularly likely to affect the thin, tightly spaced interconnect lines of deep-submicron designs.
Electromigration is an atomic transport process which results from momentum transfer to the constituent metal atoms due to collisions with the current conduction electrons. As atoms electromigrate, there is a depletion of material ``upstream'' and an accumulation ``downstream'' at sites of flux divergence. This can lead to void formation and growth at points of material depletion causing a large increase in electrical resistance and, where there is material accumulation, to dielectric cracking and the formation of an extrusion resulting in a short between adjacent lines.
Because the phenomenon does not manifest itself until a circuit has been operated for months, or even years, electromigration cannot be prevented by product testing.

Blech [47,48,49] was one of the first to explain the origin of the electromigration phenomena. In his experiments he discovered a critical product of interconnect line length and current density, below which no electromigration failure would be observed. Kirchheim [50] proposed a physically based model in which generation of stress in the grain boundaries during electromigration is caused by annhiliation and generation of vacancies. Korhonen [51] proposed another physics based analytical model for mechanical stress evolution during electromigration in a confined metal line described by a one-dimensional equation.

Experimental observations of void evolution in interconnect lines using *ex situ* and *in situ* transmission and scanning electron microscopy have significantly improved our understanding of the various failure mechanisms in interconnect lines, for example [52,8,53,54,55].

Voids often nucleate at the heterogenities occurring at a line edge. The voids then grow, migrate, and change shape due to vacancy diffusion driven by a combination of electron wind and the residual stress field.
Various analytical and numerical models for the simulation of void evolution due to electromigration and residual stress in the interconnect line have been developed in the past [56,57,58,59,60,61,62,63,64].
The significance of void evolution simulation lies in the fact that only through a sufficiently good description of the void metal surface one can predict the influence of an evolving void on the overall resistance of the interconnect.

Copper metalization offers significant performance and reliability improvement compared with aluminum metalization, but it presents numerous integration and reliability challenges. Since copper readily diffuses into silicon and most dielectrics, copper leads must be encapsulated with metallic (such as Ta, TaN) and dielectric (such as SiN, SiC) diffusion barriers in order to prevent corrosion and electrical leakage between adjacent metal leads.

The electromigration resistivity of bulk copper is known to be larger compared to aluminum. However, failure times measured on integrated copper interconnects strongly depend on the used integration scheme and the degree of process control.

An ultimative hope of integrated circuits designers today is to have a computer program at hand which predicts the behavior of thin film metalizations under any imaginable condition.
Contemporary integrated circuits are often designed using simple and conservative design rules to ensure that the resulting circuits meet reliability goals.
This precaution leads to reduced performance for a given circuit and metalization technology.
Some of the commercial and in-house electromigration reliability simulators used today are BERT [65], Railmill [66] and iTEM [67].
Probably the most widely known of these tools is BERT (Berkeley Reliability Tools) which calculates the current density distribution in the whole circuit layout and then applies this result to a set of formulas [65,68] for estimating interconnect time to failure. The time to failure calculation is based on very simple physical models depending on the number of parameters which must be determined experimentally [68]. Another weak point of this state of the art simulator is that it does not take into account the influence of mechanical stresses which were shown to be quite important [69].

- 4.1 Integrating Void Pre-Nucleation and Void Evolution
- 4.2 The Physics of Electromigration
- 4.3 Electromigration TCAD Solutions

- 4.4 Prediction of the Voids Nucleation Sites
- 4.4.1 Korhonen's Model
- 4.4.2 Analytical Solution of Korhonen's Equation
- 4.4.3 The Sink/Source Term
- 4.4.4 An Explanation of Black's Law
- 4.4.5 Sarychev's Model
- 4.4.6 Finite Element Discretization of the Basic Equation

- 4.5 Void evolution and Interconnect Resistance Change Models
- 4.5.1 Theoretical Formulation
- 4.5.2 The Diffuse Interface Model
- 4.5.3 Numerical Implementation
- 4.5.4 Setting of the Initial Order Parameter Profile and Initial Grid Refinement
- 4.5.5 Finite Element Scheme
- 4.5.6 Maintaining the Grid during Simulation
- 4.5.7 Grid Adaptation
- 4.5.8 Solving Procedure

- 4.6 Simulation Results

H. Ceric: Numerical Techniques in Modern TCAD