7.1 The Transistor Capacitor Memory Cell

The most common design for ferroelectric non-volatile memory is similar to the classical DRAM structure. It consists of a capacitor used for information storage and a transistor for the read and write operations. Such cells can be fabricated by using a conventional LSI CMOS process and adding the capacitor afterwards in another layer above the transistor [KTM+97], thus leading to the structure sketched in Fig. 7.2.

Figure 7.2: Cross section of a stacked transistor-capacitor structure

Starting out from this basic cell two different circuit designs are used, namely a double cell and a single cell design.