Downscaling of integrated circuits to the deep submicron regime and beyond increases the influence of interconnects on circuit behavior drastically. Parasitic effects are becoming more and more important as devices get faster and line widths smaller. These effects become the limiting factor for further improvements of circuit speed. An important part of interconnect analysis is the extraction of parameters, e.g. capacitance extraction , or resistance analysis.
The high performance SAP package [113,114], reviewed in Section 4.4.1, has been developed for these tasks, especially for thermal (STAP) and capacitive (SCAP) problems. This package was manually tuned to yield excellent performance and portability but requires a considerable amount of maintenance by the development group. The here presented approach is based on GSSE modules. Two examples from this area are analyzed in the following sections. A comprehensive performance analysis is also given, whereby the next section introduces an important extension of the smart analysis package known as structure modeling.