7.5 Resistance of Interconnect Wires

Metal wires are also subject to defects. Besides electromigration problems, shorted lines and too narrow lines (or even opens) are also cause of integrated circuit failure. These, in turn, are sometimes related with lithographic issues. Another associated problem is in integrated circuit power distribution lines for which the current was underestimated by the layout designer, leading to very high current densities. We can predict these problems by performing a lithography simulation as explained in Chapter 3 followed by an electrical simulation. Besides extracting the resistance of the wire, it is important to know the current density flowing in it.

Using the imaging system described, some eventually too narrow line faults where reported by the lithography tools for the layout of Figure 3.1, when the imaging system described in Section 3.4.2 is used.

Figure 7.12: Part of the three-dimensional model of the layout in Figure 3.1.

In Figure 7.12 we show a part of the three-dimensional model, where an electrical simulation was done. We observed that the current density in some places is 2 times larger than that for structures where lithography is not taken into account. The corresponding voltage drop along some lines is also too high as it is shown in Figure 7.13. We concluded that the layout, with some automatically routed nets in METAL2, must be modified, and the problems predicted by the lithography analyzer were confirmed.

Figure 7.13: The potential distribution along a interconnection wire of the layout in Figure 3.1 where problems were reported by the lithography tools.