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4.1 Usage of Layout Data

This section demonstrates how more complex polygons are added to the geometric primitives from the previous chapter. These polygons are assigned to different layers in the layout file, which correspond to different stages in the manufacturing process.

Figure 4.1: Layout of a DRAM cell.

Fig. 4.1 shows the graphical user interface of the process file editor PED [42] which was used to design the layout of a DRAM cell with a trench capacitor. A comprehensive treatise on the complex layout handling capabilities of PED can be found in the doctoral thesis of my colleague Rui Martins [41], where layout and topography simulation were used as tools for accurate investigations on three-dimensional capacitive and resistive effects in interconnect structures.

The interactive editor PED was initially designed for the generation of device cross-sections, when complete process recipes are not available and comprehensive process simulations not possible. In addition it was extended by facilities to handle different layers of polygons in one file, which was the basic prerequisite for the manipulation of layout information. In contrast to the device cross-sections with polygons in only one level, layouts are composed by sets of polygons assorted in different layers which are assigned to different process stages. Therefore the polygons in layout files may overlap, which requires a more sophisticated organization of the file format and the user interface, such as the assignment of symbolic names in order to be able to select overlapping polygons.

Moreover the editor allows binary operations on the masks, parameterized layouts and the specification of net names. Net-names are necessary for the generation of net lists which describe the connectivity of multi-level networks for metal lines from different layers connected by vias and plugs. The information about the connectivity is crucial for the assignment of consistent potential boundary conditions.

The different colors of the polygons in the layout from Fig. 4.1 indicate their affiliation to a specific layer. The layers denote active areas, doping regions, contacts, poly-silicon layers, and metal layers. This allows the process recipe to be formulated within a flow description which directly assigns the layers from the layout to the corresponding solid modeling and topography simulation steps with. Thus, the process flow for the simulation is the same as in manufacturing and can be run automatically without any further user interaction, once the layout and the process recipe is defined. The framework for such a process flow simulation is supplied either by high level flow description languages such as provided by SIESTA [76] or simply by using shell scripts. Both methods guarantee a fast generation of the three-dimensional structures. If the resulting structures have to be modified, this can be done easily by changing the layout or the process recipe and repeating the process flow simulation, which avoids the complicated and error-prone editing of the three-dimensional geometries. In the following this procedure will be applied to a DRAM cell and an interconnect structure.

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W. Pyka: Feature Scale Modeling for Etching and Deposition Processes in Semiconductor Manufacturing