Predictive and Efficient Modeling of Hot Carrier Degradation with Drift-Diffusion Based Carrier Transport Models

Chapter 5 HCD Modeling in LDMOS Devices

The LDMOS (laterally-diffused metal-oxide semiconductor) transistors are often the devices of choice in smart-power, mixed signal ICs, and high voltage automotive applications. The popularity of these transistors is also attributed to the fact that they are compatible with standard CMOS processing. This makes them easily integrable by adding a few extra process steps. Thus, radio frequency and mixed signal applications can be integrated along with the core logic transistors on a single chip. The desired breakdown voltage in LDMOS devices can be easily obtained if a suitable concentration of dopant species is chosen. However, the long drift regions cause an increase in the required chip surface while the low doping results in high power loss due to an increased ON-resistance. With the introduction of reduced surface field technology, LDMOS devices are better optimized and can provide high blocking voltages for shorter drift lengths and higher doping [197]. Thus, the ON-resistance is reduced leading to smaller power dissipation. However, lateral devices are more susceptible to hot-carrier degradation as the current flows at the $\mathrm {Si}\slash \mathrm {SiO_{2}}$ interface and not in the bulk as, for e.g., is the case in vertical DMOS devices.

Unfortunately, a proper treatment of carrier transport in LDMOS devices is challenging. First, due to the large dimensions of these devices as compared to nanoscale CMOS transistors, the simulation mesh contains a large number of elements $\backsim$ 10,000 [26]. Second, this transistor usually has a bird’s beak/STI corner and curved interfaces, see Figure 5.1, and also high doping gradients in various regions. Finally, LDMOS transistors are operated/stressed at high voltages. In this section, the hot-carrier degradation model (Section 4.3-4.4), which uses the information about the carrier energy distribution is used to represent HCD data measured in n- and p-channel LDMOS transistors. The analytical (Section 4.3) and ViennaSHE based versions of the model are compared to show that both approaches can capture HCD. Particular attention is paid to study the role of the cold fraction of the carrier ensemble. The validity of the model is checked by neglecting the effect of cold carriers in HCD modeling in the case of LDMOS devices stressed at high voltages. Finally, it is shown that even in high-voltage devices stressed at high drain voltages the thermalized carriers still have a substantial contribution to HCD.

5.1 Experiments

To validate the model, experiments were performed using n- and p-channel LDMOS transistors. The n- and pLDMOS transistors used in this work, shown in Figure 5.1, designed on 0.35 $\,\mu$ m and 0.18 $\,\mu$ m standard CMOS processes, respectively, have been subjected to hot-carrier stress at different combinations of gate and drain voltages $V_{\mathrm {gs}}$ and $V_{\mathrm {ds}}$ . The n-channel devices have a $\mathrm {Si}\slash \mathrm {SiO_{2}}$ interface length of $\sim$ 3.4 $\,\mu$ m (length of the drift region is 2.4 $\,\mu$ m, while the channel length is 1.0 $\,\mu$ m), and a gate length of $\sim$ 2.5 $\,\mu$ m. The p-channel transistors have an interface length of $\sim$ 4.4 $\,\mu$ m, and a gate length of $\sim$ 3.3 $\,\mu$ m.

The nLDMOS transistors were subjected to hot-carrier stress with six different combinations of drain and gate voltages $V_{\mathrm {ds}}$ , $V_{\mathrm {gs}}$ (i.e. at $V_{\mathrm {gs}}$ = 2.0 $\,$ V and $V_{\mathrm {ds}}$ = 18, 20, 22 $\,$ V; $V_{\mathrm {ds}}$ = 20 $\,$ V and $V_{\mathrm {gs}}$ = 1.2, 1.5, 2.0 $\,$ V) at room temperature for stress times up to $\sim$ 1 $\,$ Ms. As for the pLDMOS devices, they were stressed at $V_{\mathrm {ds}}$ = $-$ 50 $\,$ V and $V_{\mathrm {gs}}$ = $-$ 1.5, $-$ 1.7 $\,$ V for stress times up to $\sim$ 40 $\,$ ks. To monitor HCD, the normalized changes in the linear drain current $\Delta I_{\mathrm {d,lin}}(t)$ (at $V_{\mathrm {ds}}$ = 0.1 $\,$ V and $V_{\mathrm {gs}}$ = 3.6 $\,$ V) and the saturation drain current $\Delta I_{\mathrm {d,sat}}(t)$ (at $V_{\mathrm {ds}}$ = 10 $\,$ V and $V_{\mathrm {gs}}$ = 3.6 $\,$ V) were recorded as a function of stress time for nLDMOS devices. The degradation of the threshold voltage $\Delta V_{\mathrm {t}}(t)$ was also recorded for all stress conditions using the maximum transconductance method. For the pLDMOS, $\Delta I_{\mathrm {d,sat}}(t)$ at $V_{\mathrm {ds}}$ = $-$ 50 $\,$ V and $V_{\mathrm {gs}}$ = $-$ 2.5 $\,$ V was monitored. The relative drifts in the currents at any time $t$ are defined as:

$(5.1) \begin{equation} \Delta I_{\mathrm {d}}(t)=\frac {I_{\mathrm {d}}(t)-I_{\mathrm {d}}(0)}{I_{\mathrm {d}}(0)} \end{equation}$

while the relative threshold voltage shifts are defined as:

$(5.2) \begin{equation} \Delta V_{\mathrm {t}}(t)=\frac {V_{\mathrm {t}}(t)-V_{\mathrm {t}}(0)}{V_{\mathrm {t}}(0)} \end{equation}$