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Predictive and Efficient Modeling of Hot Carrier Degradation with Drift-Diffusion Based Carrier Transport Models

Chapter 7 On the Limits of Drift-Diffusion Based HCD Modeling

In this chapter, the limits of applicability of the drift-diffusion (DD) based model for hot-carrier degradation (HCD) described in Chapter 4 are studied. In [34] it was suggested that the DD scheme is applicable for describing carrier transport in devices with gate lengths longer than 0.5 \( \mu \)m. However, as shown in [29], drift-diffusion and even hydrodynamic approaches can be inadequate for modeling HCD in nMOSFETs with gate lengths of 2.0 \( \mu \)m. Thus, in this context, the analysis of the limits of the validity of the DD-based model is a very important task. To investigate the limits of the DD-based HCD model, in this work planar nMOSFETs with identical topology but different gate lengths of 2.0, 1.5 and 1.0 \( \mu \)m are used. These devices were generated with the Sentaurus process simulator [198]. The BTE solution produced by the deterministic BTE solver ViennaSHE is employed as reference [204]. While applying the DD- and SHE-based versions of the HCD model to planar nMOSFETs, the typical stress voltages for these transistors have been used which are way lower than compared to the LDMOS devices, i.e. \( V_{\mathrm {ds}} \) = 7.5 \( \, \)V and \( V_{\mathrm {gs}} \) = 2.5 \( \, \)V, see [141, 171, 205]. For all the devices, the electron DFs, interface state density profiles \( N_{\mathrm {it}}(x) \), and degradation traces \( \Delta I_{\mathrm {d,lin}}(t) \) as well as \( \Delta I_{\mathrm {d,sat}}(t) \) (for up to 50 \( \, \)ks) are simulated.

7.1 Model Results for Scaled Devices

Figure 7.1 summarizes the simulated electron energy distribution functions for 2.0, 1.5 and 1.0 \( \, \)µm nMOS devices obtained with ViennaSHE and the DD-based approach at different lateral coordinates along the channel. At low and moderate energies the DFs computed with the analytic approach, Equation 4.22, reasonably mimic the DFs obtained from a BTE solution with ViennaSHE. However, at higher energies, the curvatures of the DFs evaluated with the two approaches are different. It can be seen that the accuracy deteriorates for shorter channel lengths. On the other hand, the occupation numbers at these energies have already dropped by several orders of magnitude, and it is not obvious whether this discrepancy in the DFs translates into a sizable error in the interface state profiles \( N_{\mathrm {it}}(x) \) and the \( \Delta I_{\mathrm {d,lin/sat}} \) degradation traces.

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Figure 7.1: The electron distribution functions at different lateral positions along the channel for the nMOSFET with \( L_{\mathrm {G}} \) = 1.0 \( \,\mu \)m simulated with ViennaSHE and the DD-based version of the model.

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Figure 7.2: Same as Figure 7.1 but with \( L_{\mathrm {G}} \) = 1.5 \( \,\mu \)m.

To check the effect of discrepancy in the DFs on the device degradation traces in greater detail the acceleration integrals are plotted, which determine the corresponding rates, for the SC- and the MC-mechanism simulated along the \( \mathrm {Si}\slash \mathrm {SiO_{2}} \) interface with both versions of the model, see Figure 7.6. For the \( 2\mu \)m device the bond breakage rates for the SC- and MC-process are almost the same. This reflects the good agreement of the DFs in Figure 7.1.

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Figure 7.3: Same as Figure 7.1 but with \( L_{\mathrm {G}} \) = 2.0 \( \,\mu \)m.

For the shorter structures, the acceleration integrals of both mechanisms calculated with the two versions of the model are significantly different. However, since in these devices the interface state profiles \( N_{\mathrm {it}}(x) \), and therefore also the degradation, are mainly determined by the SC-process, the DD-based version of the model should be able to properly capture the HCD traces for the \( 1.5\mu \)m structure. The situation deteriorates for the smaller nodes. Although the contribution of the MC-mechanism is properly represented by the simplified

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Figure 7.4: The acceleration integrals for the SC- and the MC-process calculated from the DFs obtained from the DD-based model (solid lines) and ViennaSHE (dashed lines) for \( V_{\mathrm {ds}} \) = 7.5 \( \, \)V and \( V_{\mathrm {gs}} \) = 2.5 \( \, \)V for the nMOSFET with \( L_{\mathrm {G}} \) = 1.0 \( \,\mu \)m.

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Figure 7.5: Same as Figure 7.4 but for \( L_{\mathrm {G}} \) = 1.5 \( \,\mu \)m.

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Figure 7.6: Same as Figure 7.4 but for \( L_{\mathrm {G}} \) = 2.0 \( \,\mu \)m.

approach, the bond breakage rates of the SC-process are profoundly underestimated. While the SHE-based version predicts a significant build up of interface states in the channel, triggered by the interplay between the SC- and MC-mechanism, which is not adequately described by the DD-based approach.

In order to investigate the mismatch of the DFs (Figure 7.1) and the impact of the bond breakage rates (Figure 7.6) onto the interface trap profiles, the \( N_{\mathrm {it}}(x) \) values simulated with both versions of the model are plotted in Figure 7.7. One can see that in the case of the longest device, i.e. the \( 2\mu \)m nMOSFET structure, the \( N_{\mathrm {it}}(x) \) profiles are very similar. This

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Figure 7.7: The \( N_{\mathrm {it}}(x) \) profiles evaluated for the three nMOSFETs with gate lengths \( L_{\mathrm {G}} \) = 1.0 \( \,\mu \)m by both versions of the model for stress times of 10 \( \, \)s and 40 \( \, \)ks.

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Figure 7.8: Same as Figure 7.7 but for \( L_{\mathrm {G}} \) = 1.5 \( \,\mu \)m.

is caused by the fact that the electron DFs are properly approximated by the DD-based model as can be seen in Figure 7.1. The situation starts to change for the shorter structure with \( L_{\mathrm {G}} \) = 1.5 \( \,\mu \)m, i.e. agreement between both models deteriorates. For the device with \( L_{\mathrm {G}} \) = 1.5 \( \,\mu \)m the discrepancy between the \( N_{\mathrm {it}}(x) \) values is visible at \( N_{\mathrm {it}}\sim \, \)10 \( ^{8} \)cm \( ^{-2} \). The \( N_{\mathrm {it}} \) peak at the drain side becomes broader and is shifted towards the channel as can be concluded from Figure 7.6. The DD-based approach is not able to capture this trend. Since \( N_{\mathrm {it}} \) values of \( \sim \, \)10 \( ^{8} \)cm \( ^{-2} \) do not contribute to the total device degradation, a significant deviation between the \( \Delta I_{\mathrm {D,lin/sat}} \) degradation curves simulated by the two model versions is not expected. For the shortest device, however, the interface trap densities already differ by about \( \sim \, \)10 \( ^{12} \)cm \( ^{-2} \). Such large values provide a considerable contribution to HCD and lead to a visible discrepancy between the drain current degradation traces.

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Figure 7.9: Same as Figure 7.7 but for \( L_{\mathrm {G}} \) = 2 \( \,\mu \)m.

As a result, best correspondence between \( \Delta I_{\mathrm {D,lin/sat}} \) obtained with the SHE- and DD-based models is achieved for the \( 2.0\mu \)m nMOSFET, see Figure 7.11. Note, however, that

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Figure 7.10: The \( \Delta I_{\mathrm {d,lin}}(t) \) and \( \Delta I_{\mathrm {d,sat}}(t) \) degradation curves obtained with SHE(symbols) - and DD-based (lines) versions model for n-MOSFET with \( L_{\mathrm {G}} \) = 1 \( \,\mu \)m.

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Figure 7.11: Same as Figure 7.10 but for \( L_{\mathrm {G}} \) = 1.5 \( \,\mu \)m.

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Figure 7.12: Same as Figure 7.10 but for \( L_{\mathrm {G}} \) = 2 \( \,\mu \)m.

even for this device the analytic model leads to lower \( \Delta I_{\mathrm {D,lin/sat}} \) values at short stress times. This is because, as shown in [26, 147], short-term HCD is determined by the DFs at the drain, which are underestimated by the DD-based model, see Figure 7.1.

The same argument also holds for the 1.5 \( \,\mu \)m device where the agreement is still reasonable. Hot carrier degradation is slightly underestimated over the whole stress time range due to the mismatch of the interface state profiles visible in Figure 7.7. For the shortest device the DD-based model completely fails to properly reproduce the data evaluated with the full model. This already becomes evident in Figures 7.1, 7.6, and 7.7 where one can see that the DD-based model is not capable of reasonable mimicking the ViennaSHE results, respectively the big discrepancies between the shape of the interface state profiles.

To conclude, the drift-diffusion based hot-carrier degradation model, created for high voltage LDMOS devices, is found to work reasonably well for MOSFETs with channels longer than \( 1.5\mu \)m. In such devices, the model was able to represent the carrier distribution functions, bond breakage rates, interface state density profiles, and changes of device characteristics such as the saturation and drain currents. However, the model does not work very well for smaller nodes. The reason is that the DD-based model is not able to capture more complicated DF shapes visible in shorter devices. This is especially pronounced at high energies because the DFs simulated with ViennaSHE and by the DD-based HCD model have different curvatures. In the case of the \( 2\mu \)m device the curvature change occurs only when the DF values have dropped by several orders of magnitude, and therefore this discrepancy does not translate into mismatches between bond breakage rates, \( N_{\mathrm {it}}(x) \) profiles and \( \Delta I_{\mathrm {d,lin}}(t) \), \( \Delta I_{\mathrm {d,sat}}(t) \) degradation traces.

As for shorter devices, the discrepancy in the DF curvature appears at higher population numbers, and thus is related to more pronounced errors. In the device with \( L_{\mathrm {G}} \) = 1.5 \( \,\mu \)m this results in a mismatch in the \( N_{\mathrm {it}}(x) \) profiles visible at 10 \( ^{8} \)cm \( ^{-2} \), and thereby does not substantially impact the \( \Delta I_{\mathrm {d,lin}}(t) \), \( \Delta I_{\mathrm {d,sat}}(t) \) changes. In the shortest nMOSFET used, \( L_{\mathrm {G}} \) = 1 \( \,\mu \)m, \( N_{\mathrm {it}} \) values differ severely at values of 10 \( ^{12} \)cm \( ^{-2} \), and hence the changes of the linear and saturation drain currents simulated with the two versions of the model are completely inconsistent.