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Predictive and Efficient Modeling of Hot Carrier Degradation with Drift-Diffusion Based Carrier Transport Models

5.6 Modeling the Degradation in pLDMOS Transistor

The validity of the model beyond the nLDMOS transistor was tested by following a similar procedure for calculating DFs, \( N_{\mathrm {it}}(x) \) profiles, and drain current degradation curves for an pLDMOS. Even in this case, the DFs obtained from the DD-based approach and SHE method are quite similar as was shown in Figure 5.4. The DF in the case of the pLDMOS transistor have a slightly different appearance in the drain region as compared to the nLDMOS, lacking the cold carrier part (Figures 5.3 and 5.4), while near the STI corner, they look similar as for the bird’s beak region in the nLDMOS. This is due to differences in the architectures (and even different technology nodes) of the n- and p-channel LDMOS transistors used. Another reason which leads to the different shapes of the DFs for the pLDMOS devices is the different stress conditions for n- and p-channel transistors. Due to the high stress voltages used for the pLDMOS ( \( V_{\mathrm {ds}} \) = \( - \)50 \( \, \)V) as compared to the nLDMOS ( \( V_{\mathrm {ds}} \) = 20 \( \, \)V), no high concentration of cold carriers is present at the drain in the former case. As a result, the DFs for the pLDMOS lacks the Maxwellian low energy fragment which

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Figure 5.19: Interface state density profiles obtained with SHE- and DD-based models for the pLDMOS transistor. The stress voltages are \( V_{\mathrm {ds}} \) = \( - \)50 \( \, \)V and \( V_{\mathrm {gs}} \) = \( - \)1.5 \( \, \)V applied for stress times 10 \( \, \)s and 40 \( \, \)ks.

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Figure 5.20: Comparison of the change in the saturation drain current in the pLDMOS transistor obtained from experiments and simulations, using the SHE- and DD-based models for stress voltages \( V_{\mathrm {ds}} \) = \( - \)50 \( \, \)V and \( V_{\mathrm {gs}} \) = \( - \)1.5, \( - \)1.7 \( \, \)V for stress times up to 40 ks.

was seen in the DF corresponding to the nLDMOS. The DFs are then used to calculate the \( N_{\mathrm {it}}(x) \) profiles for the entire lateral coordinate of the pLDMOS transistor. The \( N_{\mathrm {it}}(x) \) profiles are plotted in Figure 5.19. To demonstrate that the model works well for the pLDMOS device too, the \( \Delta I_{\mathrm {d,sat}}(t) \) obtained from simulations is compared against the experimental data in Figure 5.20. As can be seen, the simulated curves agree well with the experiments.