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Predictive and Efficient Modeling of Hot Carrier Degradation with Drift-Diffusion Based Carrier Transport Models

5.5 Modeling the Degradation in nLDMOS Transistor

The DD-based scheme is able to represent the carrier distribution functions for the source and channel regions. Note that in these device sections the DFs are not severely perturbed

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Figure 5.6: The acceleration integral in an nLDMOS calculated using the DFs obtained with the DD-based model and using ViennaSHE for \( V_{\mathrm {ds}} \) = 20 \( \, \)V, \( V_{\mathrm {gs}} \) = 2 \( \, \)V for the single- and multiple-carrier processes.

from equilibrium. As already shown in Figure 5.3, the agreement between the non-equilibrium DFs is also good, especially near the bird’s beak of the nLDMOS transistor. As for the drain region, a small discrepancy is visible at high energies. At these high energies, however, the DF has dropped by more than 20 orders of magnitude and this dis-

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Figure 5.7: Interface state density profiles in an nLDMOS evaluated with the DD- and SHE-based models for stress voltages \( V_{\mathrm {ds}} \) = 20 \( \, \)V, \( V_{\mathrm {gs}} \) = 2 \( \, \)V applied for 10 \( \, \)s and 1 \( \, \)Ms.

crepancy does not transform into a significant error of the model. To prove this, the acceleration integrals calculated by Equation 4.29 are plotted for both the single- and multiple-carrier processes. Figure 5.6 shows that the acceleration integrals computed with the SHE- and DD-based approaches are quite similar, and thus the discrepancy in the DFs at high energies, visible for the case of the drain region, is insignificant. Figure 5.6 also demonstrates that the multiple-carrier process plays an important role in large devices such as the nLDMOS transistor and should be considered in the model.

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Figure 5.8: The electron and hole concentrations in an nLDMOS as a function of the coordinate \( y \) perpendicular to the \( \mathrm {Si}\slash \mathrm {SiO_{2}} \) interface evaluated near the drain region, the bird’s beak, and in the channel.

This is because the peak in the acceleration integral vs the lateral device coordinate curve at \( x \) \( \sim \)2.8 \( \,\mu \)m corresponds to the multiple-carrier bond breakage process indicating that the MC-mechanism is the major source of defect creation near the source region of the device.

The \( N_{\mathrm {it}}(x) \) profiles simulated using the SHE- and DD-based approaches for the entire lateral coordinate range and for 10 \( \, \)s and 1 \( \, \)Ms are presented in Figure 5.7. It can be seen from Figures 5.3 and 5.6 that the carriers near the drain are rather hot and both the single- and multiple-carrier mechanisms are saturated, thus leading to an \( N_{\mathrm {it}} \) peak at the drain region. Another peak is pronounced in the vicinity of the bird’s beak which is due to the single-carrier process as the rate of the multiple-carrier process (Figure 5.6) is negligible in this region. The third \( N_{\mathrm {it}} \) maximum located in the channel at \( x \) \( \sim \) 2.8 \( \,\mu \)m stems from the common action of the multiple-carrier mechanism of the bond dissociation and the interaction of the dipole moment of the bond with the electric field [26]. The role of this \( N_{\mathrm {it}} \) peak in the channel is also important for the representation of the overall device degradation.

It is worth discussing that only the electron induced portion of the degradation is considered because the hole concentration at the interface is very low. Figure 5.8 shows the hole concentration plotted as a function of the coordinate orthogonal to the \( \mathrm {Si}\slash \mathrm {SiO_{2}} \) interface evaluated for three different positions in the nLDMOS devices: at the drain, in

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Figure 5.9: The experimental change in the saturation and the linear drain currents plotted vs. simulations obtained with the SHE- and DD-based versions of the model for a gate voltage \( V_{\mathrm {gs}} \) = 2 \( \, \)V and drain voltage \( V_{\mathrm {ds}} \) = 18 \( \, \)V in an nLDMOS transistor.

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Figure 5.10: Same as Figure 5.9 but for \( V_{\mathrm {gs}} \) = 2 \( \, \)V and \( V_{\mathrm {ds}} \) = 20 \( \, \)V.

the channel, and near the bird’s beak. For comparison, the electron concentration profiles are also plotted in Figure 5.8. One can see that the hole concentration at the interface does

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Figure 5.11: Same as Figure 5.9 but for \( V_{\mathrm {gs}} \) = 2 \( \, \)V and \( V_{\mathrm {ds}} \) = 22 \( \, \)V.

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Figure 5.12: The relative change in the linear drain current simulated with the DD-based version of the model for an nLDMOS transistor. One can see that if the mobility degradation is not considered, the change in current can be severely underestimated. For instance, at a stress time of 1Ms the error in \( I_{\mathrm {d,lin}}(t) \) is 27 \( \% \).

not exceed \( 10^{5}\,\mathrm {cm}^{-3} \), i.e. around 15 orders of magnitude lower than the electron concentration. Therefore, we conclude that the contribution of holes can be neglected. The normalized experimental change of the linear and saturation drain currents simulated with

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Figure 5.13: The relative change in \( I_{\mathrm {d,sat}} \) simulated with the DD-based version of the model for an nLDMOS transistor. At a stress time of 1Ms the error in \( I_{\mathrm {d,sat}}(t) \) is 33 \( \% \).

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Figure 5.14: The change in the saturation and linear drain currents: experiment vs. the DD-based model in an nLDMOS. Results are obtained for a drain voltage \( V_{\mathrm {ds}} \) = 20 \( \, \)V and gate voltage \( V_{\mathrm {gs}} \) = 1.2 \( \, \)V.

the SHE- and DD-based versions of the HCD model is plotted against the experimental data in Figures 5.9, 5.10 and 5.11 for a fixed gate voltage of \( V_{\mathrm {gs}} \) = 2 \( \, \)V and a series of three

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Figure 5.15: Same as Figure 5.14 but for \( V_{\mathrm {ds}} \) = 20 \( \, \)V and \( V_{\mathrm {gs}} \) = 1.5 \( \, \)V.

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Figure 5.16: Same as Figure 5.14 but for \( V_{\mathrm {ds}} \) = 20 \( \, \)V and \( V_{\mathrm {gs}} \) = 2 \( \, \)V.

different drain voltages: \( V_{\mathrm {ds}} \) = 18, 20, and 22 \( \, \)V. One can see that the agreement between the experimental results and the simulated data is very good. It is important to emphasize that the \( \Delta I_{\mathrm {d,lin}}(t) \) and \( \Delta I_{\mathrm {d,sat}}(t) \) curves obtained with the SHE- and DD-based versions of

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Figure 5.17: Comparison of the change in the threshold voltage obtained from experiments and simulation in an nLDMOS, using the SHE- and DD-based models, for stress voltages \( V_{\mathrm {gs}} \) = 2 \( \, \)V and \( V_{\mathrm {ds}} \) = 20 and 22 \( \, \)V for stress times up to 1 \( \, \)Ms.

the model are almost the same within the whole experimental time window. This makes the latter version attractive for efficient and predictive HCD simulations of nLDMOS devices. Figures 5.12 and 5.13 show the \( \Delta I_{\mathrm {d,lin}}(t) \) and \( \Delta I_{\mathrm {d,sat}}(t) \) traces simulated with the DD-based version of the model with and without the effect of mobility degradation (see Equation 4.39). One can see that for the entire stress time window the current degradation simulated considering only the electrostatics perturbation due to the interface state build-up is substantially underestimated.

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Figure 5.18: The threshold voltage shift vs. stress time: a comparison between experiment and simulation with the DD-based model for a fixed drain voltage \( V_{\mathrm {ds}} \) = 22 \( \, \)V and two different gate voltages \( V_{\mathrm {gs}} \) = 1.2 and 2 \( \, \)V.

To check the DD-based model in greater detail, the normalized changes in the linear and saturation drain currents simulated exclusively with the DD-model for a fixed \( V_{\mathrm {ds}} \) = 20 \( \, \)V and three different \( V_{\mathrm {gs}} \) = 1.2, 1.5, and 2.0 \( \, \)V are plotted in Figures 5.14, 5.15 and 5.16. It can be concluded that the agreement between the experimental data and the degradation traces is very good. This is also the case for the threshold voltage shifts \( \Delta V_{\mathrm {t}}(t) \) for \( V_{\mathrm {gs}} \) = 2 \( \, \)V and \( V_{\mathrm {ds}} \) = 20 \( \, \)V and 22 \( \, \)V obtained with both versions of the HCD model and plotted vs. the measured \( \Delta V_{\mathrm {t}}(t) \) traces, as shown in Figure 5.17. Again, as in the case of the drain current degradation, the DD-based model is applied to represent \( \Delta V_{\mathrm {t}}(t) \) traces for \( V_{\mathrm {ds}} \) = 22 and \( V_{\mathrm {gs}} \) = 1.2 and 2 \( \, \)V without using the ViennaSHE DFs as a reference, see Figure 5.18, and a good agreement between experiments and theory is obtained. It is important to emphasize that all above simulations were carried out with the same parameter set.