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1 The Transistor

With the first analysis of electricity more than 200 years ago and the enhanced insight into the physical process of electric charge manipulation the way to revolutionary technological inventions was enabled. Although many inventions were considered fundamental research and initially ignored by industry, some of these have eventually changed our way of living and as such are of enormous economic importance. A rather prominent example is the transistor, which is one of the key inventions of modern society, arguably comparable to the domestication of fire and the invention of the wheel.

As a result of basic research on the physics of solids, transistors were able to replace vacuum tubes in the 1950s. In the following, this led to the development of the integrated circuit and the microprocessor, which are at the heart of modern electronics. Thus, transistors paved the way for a new generation of powerful and efficient electronic devices with a seemingly unlimited number of applications in everyday life. As a consequence of the continuous improvement of their performance, modern technologies have enabled numerous innovative ways of global networking by connecting things and people, optimizing work flows as well as saving valuable resources.

The economic importance of these new technologies and the pressure to keep production costs low have been the driving forces for the development and improvement of the transistor. In 1965, Moore predicted an exponential relationship between circuit complexity (number of transistors per area unit) and time, by stating that “the complexity will double annually." This prediction has in the meantime been revised to a doubling every two years [1], resulting in over 5 billion transistors being processed on a single chip today. As a consequence of the complexity increase, transistors have been downscaled to the deca-nanometer regime during the past decades, which has resulted in reliability issues, power loss and instabilities as the physical limits are approached.

As an introduction to this thesis, a short overview of the consequences that have resulted from downscaling combined with the motivation to study degradation mechanisms in transistors is given.

1.1 The Transistor in Digital Circuits

Since the transistor has been invented, an enormous diversity of transistor technologies has arisen, each of them developed for a different purpose. As examples for the numerous purposes, the basic function of a bipolar junction transistor (BJT) is to amplify current in electronic circuits, the insulated-gate bipolar transistor (IGBT) is a power semiconductor device primarily used as an electronic switch in power electronics and the field-effect transistor (FET) acts like a switch in digital circuits. Particularly the metal-oxide-semiconductor field-effect transistor (MOSFET) is one widely used transistor technology in digital circuits due to the achievable short switching times and the nearly loss-less control at low frequencies. In the present work, MOSFETs were studied exclusively.

Figure 1.1: Lateral planar MOSFET used in complementary MOS (CMOS) technology: The cross section of a p- channel MOSFET (pMOSFET) is shown in the left panel. Two highly p-doped source and drain regions separated by an n-doped body region (e.g. Si) and an insulating layer (e.g. silicon oxynitride \ch{SiON}) separating the gate contact from the body. The right panel shows a circuit schematics of a CMOS inverter, which is a widly used application of MOSFETs in digital circuits.

The MOSFET in digital circuits can be compared to a switch realized by modifying the conductivity properties of semiconductors. Figure 1.1 shows the cross section of a pMOSFET containing two highly p-doped regions, source and drain, separated by an n-doped body region. An insulating layer (e.g. amorphous silicon oxynitride \ch{SiON}) is sandwiched between the gate and the body, separating them from each other. Therefore, the gate electrode (metal or polysilicon), the insulating layer and the substrate form the MOSFET capacitor, which prevents a current flow and enables a loss-less control of the MOSFET. Assuming that this capacitor is ideal (no charges in the oxide, resistivity of the oxide is infinite) the MOSFET function can be explained based on the band diagrams shown in Figure 1.2.

In the case of a pMOSFET, a positive gate voltage (\( V_\mathrm {G} \)) accumulates the majority carriers of the substrate, which are electrons, in a layer near the oxide/substrate interface. In the band diagram shown in Figure 1.2, this means that the conduction band (\( E_\mathrm {C} \)) bends down towards the Fermi level (\( E_\mathrm {F} \)). When sweeping \( V_\mathrm {G} \) towards zero, the MOSFET reaches its flatband condition for \( V_\mathrm {G} \)\( = \) 0 V (ideal capacitor, otherwise the contact voltage must be considered), where the majority and minority carriers are in thermal equilibrium. By applying a low negative \( V_\mathrm {G} \) the majority carriers are forced away from the interface and therefore a depletion layer near the interface forms, which results in a bending up of the bands and the intrinsic energy (\( E_\mathrm {i} \)) moves closer to \( E_\mathrm {F} \). With further increasing negative \( V_\mathrm {G} \), the depletion layer is populated by minority carriers until \( V_\mathrm {G} \) exceeds a certain threshold voltage (\( V_{\mathrm {th}} \)) and the concentration of minority carriers is high enough to form a thin inversion layer near the interface. In the band diagram the inversion mode can be explained by a crossing of \( E_\mathrm {i} \) and \( E_\mathrm {F} \) where the minority carriers exceed the majority carriers at the interface. In this context it has to be mentioned, that \( V_{\mathrm {th}} \) is defined as a microscopic parameter which indicates the transition to the inversion mode.

Figure 1.2: The energy band diagrams for an ideal MOSFET capacitor: Under different bias conditions the MOSFET can be driven from accumulation (left) to inversion (right). Top: n-channel MOSFET (nMOSFET) Bottom: pMOSFET

As a consequence, if the supply voltage (\( V_{\mathrm {DD}} \)) is applied between the drain and the source, \( V_\mathrm {G} \) controls the drain current (\( I_\mathrm {D} \)) as seen in the transfer characteristics (\( I_\mathrm {D} \)-\( V_\mathrm {G} \)) shown in Figure 1.3 for an nMOSFET. If \( V_\mathrm {G} \)\( =0 \) V, the MOSFET is in its off-state and current flow is inhibited because of the reverse biased p-n junction. As soon as a positive \( V_\mathrm {G} \) is applied and increased an \( I_\mathrm {D} \) can flow due to the inverted interface until it reaches the saturation which corresponds to the on-state of the pMOSFET. This basic function of a MOSFET makes it quite advantageous for processing of digital signals in circuits as shown in Figure 1.1 for the digital stage of a CMOS inverter. For this example, the nMOSFET is in its on-state in the case that the input is at a digital high level while the pMOSFET is in its off-state. As a result, the output voltage is at ground (digital low level). By contrast, if the input voltage is near zero, the nMOSFET is in its off-state while the pMOSFET is conductive, which results in an output voltage at \( V_{\mathrm {DD}} \) (digital high level). This corresponds to inverting a digital signal.

Figure 1.3: Typical transfer characteristics of an nMOSFET: Drain current \( I_\mathrm {D} \) plotted against gate voltage \( V_\mathrm {G} \) on a log-lin (red, left scale) and a lin-lin (blue, right scale) scale. Off-current (current flowing when MOSFET is switched off), subthreshold slope (slope of the subthreshold region in a log-lin plot), threshold voltage (\( I_\mathrm {D} \) where the inversion layer is formed) and on-current (current flowing in the on-state) are the most important parameters characterizing the \( I_\mathrm {D} \)-\( V_\mathrm {G} \).

Due to the imperfections of real devices, the CMOS technology allows for deviations from the perfect digital low level at ground and the digital high level at \( V_{\mathrm {DD}} \) by defining the first as a voltage between 0 V and \( 1 \)/\( 3 \)\( V_{\mathrm {DD}} \) and the second as a voltage between \( 2 \)/\( 3 \)\( V_{\mathrm {DD}} \) and \( V_{\mathrm {DD}} \). Thus, a reliable and proper signal processing requires digital low and high levels within these margins at a low circuit power consumption, which implies some limitations for the MOSFET design. These limitations can be explained based on the characteristics of a real device as shown in Figure 1.3. The \( I_\mathrm {D} \)-\( V_\mathrm {G} \) of a MOSFET is typically characterized by four parameters determined by materials, doping and geometry: the off-current, the sub-threshold swing (\( SS \)) (reciprocal value of the sub-threshold slope (\( S \)) in a log-lin plot), \( V_{\mathrm {th}} \) (in this case a macroscopic parameter corresponding to, e.g., the gate voltage at which a certain \( I_\mathrm {D} \) flows) and the on-current. The off-current (\( I_\mathrm {D} \)\( \neq   \)0 A at \( V_\mathrm {G} \)\( = \)0 V) is caused by leakage currents between source and drain and is inevitable. Furthermore, the switching process between off- and on-state shows switching dynamics characterized by \( V_{\mathrm {th}} \) and \( SS \) which are limited to certain minimum values. At this point it has to be mentioned that several definitions for the extraction of the macroscopic parameter \( V_{\mathrm {th}} \) exist [2] which contradicts the definition of \( V_{\mathrm {th}} \) as the gate voltage where inversion is satisfied. While \( V_{\mathrm {th}} \) as a macroscopic parameter is extracted from the transfer characteristics and is based, e.g., on an \( I_\mathrm {D} \) threshold or on the maximum transconductance, \( V_{\mathrm {th}} \) as a microscopic parameter defines the transition from accumulation to inversion. The latter depends on the lateral position due to non-uniform doping profiles along the channel.

These parameters have to meet certain requirements in order to ensure a correct interaction of the MOSFET with other circuit components. For example, clearly distinguishable digital levels require a ratio between on- and off-current which is as large as possible. This can be achieved by maximizing \( V_{\mathrm {DD}} \) while simultaneously keeping \( SS \) and \( V_{\mathrm {th}} \) as low as possible. Besides increasing the ratio, a high \( V_{\mathrm {DD}} \) would also ensure an on-current which is high enough to drive subsequent digital stages, and low \( SS \) and \( V_{\mathrm {th}} \) would enhance the switching dynamics. However, increasing \( V_{\mathrm {DD}} \) conflicts with the requirement of low power consumption since \( P \propto V_\mathrm {DD}^2 \) and, as mentioned in the previous paragraph, \( SS \) and \( V_{\mathrm {th}} \) are either fundamental limits or limited due to materials, doping and geometry of the MOSFET.

The consideration of these aspects in the fabrication process provides fundamental challenges for the design of MOSFETs in general. However, excessive scaling of the MOSFET geometries has led to further challenges.

Figure 1.4: Percolation path: A single percolation path formed by random discrete dopants (current flow shown in the uppermost layer) and contours of constant potential in a pMOSFET: Left: current flow without a disturbance due to charge exchange events caused by oxide defects. Center: reduced current flow when a defect located beside the percolation path traps a charge carrier. Right: disturbance of the current flow when a defect located directly in the center of the percolation path traps a charge carrier. [3]

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