5.1.2 High Temperature Simulations

Several groups have studied the high-temperature DC operation of AlGaN/GaN HEMTs on different substrates (sapphire [372,373,374], SiC [373], and Si [374,350]). AC measurements at elevated temperatures, however, are sparse: e.g. the temperature dependence of the cut-off frequency is compared to that of the transconductance by Akita et al. [375]. An investigation of the influence of high temperature on the microwave power performance of AlGaN/GaN HEMTs is conducted by Arulkumaran et al. [376].

The theoretical studies of GaN-based transistors at higher temperature are also rare. There are few analytical models developed [377,378,379], however, those are tailored for use in circuit simulation, not for device optimization. To our knowledge there is only one work which focuses solely on high-temperature HEMT device simulation [380], however, it relies on dated experimental data [375] and does not feature AC performance.

Based on the temperature dependent material and model parameters as discussed in Chapter 4, the simulator is calibrated with the $ L_{\mathrm{g}} =0.25 \mu\ensuremath{\mathrm{m}}$ structure (Device C in the previous section) serving as a calibration device [15]. HD electron mobility Model B is chosen for this study. The already mentioned values for the interface charges (Table 5.1) are retained, as are the other material and model parameters as e.g. the Schottky barrier height. However, it should be mentioned that the changes in the barrier height with temperature (in the range under investigation) are found to be negligibly small [381].

Using the same set of models and model parameters a $ L_{\mathrm{g}} =0.5 \mu\ensuremath{\mathrm{m}}$ benchmark device is simulated. All other device properties (layer thickness and composition and geometry) are the same. The ambient temperatures at which the devices were measured and are simulated are 300 K, 365 K, and 425 K. For the gate-variation study, two more devices with $ L_{\mathrm{g}} =0.1 \mu\ensuremath{\mathrm{m}}$ and $ L_{\mathrm{g}} =0.15 \mu\ensuremath{\mathrm{m}}$ are simulated. Also a fourth ambient temperature of 485 K is explored. DC Results

Using the values for the polarization-induced interface charges from Table 5.1 a very good agreement between measurement data and simulation results for the transfer characteristics of the calibration device is achieved (Fig. 5.12). Our setup allows for a proper modeling of the drain current also at elevated temperatures. As an example, Fig. 5.13 shows the output characteristics at 425 K. Two curves are shown for $ V_\ensuremath {\mathrm {GS}}$=2 V: without self-heating, which greatly overestimates the current; with self-heating, which delivers a significantly better match, but requires a higher computational effort. While others [382] have observed a significant threshold voltage ( $ V_\ensuremath {\mathrm {th}}$) shift, in our measurements such a shift is almost non-existent. As $ V_\ensuremath {\mathrm {th}}$ depends on the carrier density, carrier trap density and the Schottky barrier height [383], we can assume that trapping effects in the devices are also temperature-independent in this range (the carrier density change is also negligible).

Figure 5.12: Calibrated transfer characteristics (lines) versus experimental data (symbols) for $ L_\ensuremath {\mathrm {g}}=0.25 \mu $m HEMT.

Figure 5.13: Calibrated output characteristics versus experimental data (symbola) for $ L_\ensuremath {\mathrm {g}}=0.25 \mu $m HEMT at 425 K. Dot-dashed line - without self-heating, solid lines - with self-heating.

Fig. 5.14 shows the lattice temperature in the device at $ V_\ensuremath {\mathrm {DS}}$=20 V and $ V_\ensuremath {\mathrm {GS}}$=2 V bias. The area where the lattice is heated from high-energy electrons, is the high-electric field region under the drain side of the gate and the gate-extension.

Figure 5.14: Lattice temperature in the calibration device, $ V_\ensuremath {\mathrm {GS}}$=2 V, $ V_\ensuremath {\mathrm {DS}}$=20 V.

The same simulations are performed for the benchmark device. Retaining the same interface charge values, a good prediction of the threshold voltage is obtained (Fig. 5.15). Raising the ambient temperature, once again yields a good agreement between simulation results and experimental data, also for the output characteristics (shown at 425 K in Fig. 5.16).

Figure 5.15: Predicted transfer characteristics (lines) compared to measured data (symbols) for $ L_\ensuremath {\mathrm {g}}=0.5 \mu $m HEMT.

Figure 5.16: Predicted output characteristics versus experimental data for $ L_\ensuremath {\mathrm {g}}=0.5 \mu $m HEMT at 425 K.
\includegraphics[width=9.7cm]{figures/sim/temp/Out05_425L.eps} RF Results

The RF device performance is studied by small-signal AC analysis [365]. Fig. 5.17 shows the current gain $ \vert h_{21}\vert$ for the 0.25 $ \mu$m device for three temperatures. The gain decreases for higher temperatures and the simulation agrees well with the measurements. The calculated cut-off frequency $ f_\ensuremath {\mathrm {t}}$ is compared to the measured one in Fig. 5.18. In order to account for the parasitics introduced by the measurement equipment the intrinsic parameters delivered by the simulation are transformed into extrinsic ones by using a standard two-port pad parasitic equivalent circuit. The values of the circuit elements are listed in Table 4.15. As already mentioned the measured device has two gate fingers of 50 $ \mu$m width each, which leads to a higher gate capacitance due to three-dimensional parasitic effects, than the simulated single device with $ W_\ensuremath{\mathrm{g}}$=100 $ \mu$m.

Figure 5.17: Current gain $ \vert h_{21}\vert$ for $ L_\ensuremath {\mathrm {g}}=0.25 \mu $m HEMT, experimental data (solid lines) versus simulation (dashed lines).

Figure 5.18: Simulated cut-off frequency $ f_\ensuremath {\mathrm {t}}$ (lines) compared to measurements (symbols) for $ L_\ensuremath {\mathrm {g}}=0.25 \mu $m HEMT.

A very good agreement between measured and simulated S-parameters is achieved at all temperatures both for the calibration device ( $ L_{\mathrm{g}} =0.25 \mu\ensuremath{\mathrm{m}}$) and the benchmark device ( $ L_{\mathrm{g}} =0.5 \mu\ensuremath{\mathrm{m}}$). Fig. 5.19 and Fig. 5.20 compare the simulated and measured intrinsic S-parameters in the range 100 MHz$ -$26 GHz at $ V_\ensuremath {\mathrm {DS}}$=7 V and $ I_\ensuremath {\mathrm {D}}$=260 mA/mm for the $ L_{\mathrm{g}} =0.25 \mu\ensuremath{\mathrm{m}}$ HEMT at 300 K and 425 K. Fig. 5.21 and Fig. 5.22 compare predictive simulation results for the $ L_{\mathrm{g}} =0.5 \mu\ensuremath{\mathrm{m}}$ device in the same frequency range, $ V_\ensuremath {\mathrm {DS}}$=7 V, and $ I_\ensuremath {\mathrm {D}}$=130 mA/mm at 300 K and 425 K.

Figure 5.19: S-parameters for the $ L_\ensuremath {\mathrm {g}}=0.25 \mu $m device at 300 K.
Figure 5.20: S-parameters for the $ L_\ensuremath {\mathrm {g}}=0.25 \mu $m device at 425 K.

Figure 5.21: S-parameters for the $ L_\ensuremath {\mathrm {g}}=0.5 \mu $m device at 300 K.
Figure 5.22: S-parameters for the $ L_\ensuremath {\mathrm {g}}=0.5 \mu $m device at 425 K.
\includegraphics[width=10.5cm]{figures/sim/temp/S05425.eps} Gate Length Variation

The geometry of the transistors is pointed out to be an important factor for high-temperature operation. Consequently, several authors have studied the reduction of $ I_\ensuremath {\mathrm {D}}$ with rising temperature for different gate lengths e.g. [350,349]. There is agreement that for short channel devices ( $ L_{\mathrm{g}}$<$ 1 \mu$m) the carriers under the gate travel with saturation velocity. Therefore, the decrease of $ I_\ensuremath {\mathrm {D}}$ is lower, because the decrease of the velocity in the saturation region is also lower. While only submicron devices are studied, the results for $ L_{\mathrm{g}} =1.0-0.25 \mu\ensuremath{\mathrm{m}}$ structures agree well (Fig. 5.23) with the ones presented by Tan et al. [350]. However, for very small gates an even lower temperature dependence is observed. The same effect is more pronounced for the normalized $ f_\ensuremath {\mathrm {t}}$, where the devices with $ L_{\mathrm{g}} =1.0-0.25 \mu\ensuremath{\mathrm{m}}$ deliver a similar reduction of $ f_\ensuremath {\mathrm {t}}$ with temperature, while $ f_\ensuremath {\mathrm {t}}$ of the sub-quartermicron devices decreases less (Fig. 5.24). We believe that for such gate length, not only $ L_{\mathrm{g}}$ but also the gate-drain and gate-source distances and the exact geometry gain on importance, as for small gate lengths the parasitic contributions have to be scaled according to typical scaling rules in order to harvest the high-speed performance. In this case the relative contributions of the ohmic elements and thus their temperature dependence are reduced.

Figure 5.23: Simulated maximum $ I_\ensuremath {\mathrm {D}}$ ( $ V_\ensuremath {\mathrm {DS}}$=7 V) as a function of ambient temperature normalized to 300 K values.

Figure 5.24: Simulated maximum $ f_\ensuremath {\mathrm {t}}$ ( $ V_\ensuremath {\mathrm {DS}}$=7 V) as a function of ambient temperature normalized to 300 K values.

S. Vitanov: Simulation of High Electron Mobility Transistors