5.2.2 InGaN Cap Device Structure

The investigated InGaN/AlGaN/GaN device structure as described in [394] is shown in Fig. 5.56. A 3 $ \mu$m thick GaN layer is grown on a sapphire substrate. A 20 nm thick Al$ _{0.25}$Ga$ _{0.75}$N layer is deposited next: the first 5 nm undoped, 10 nm highly-doped (2$ \times $10$ ^{18}$cm$ ^{-3}$) supply layer, and 5 nm undoped material. On-top a 5 nm thick In$ _{0.2}$Ga$ _{0.8}$N layer is deposited. All layers are non-intentionally doped, except the supply layer. The gate length $ L_{\mathrm{g}} =1.9 \mu\ensuremath{\mathrm{m}}$, source gate distance is 1.5 $ \mu$m, and gate drain distance is 2.4 $ \mu$m. Three different HEMT structures are studied: the proposed novel normally-off device (Fig. 5.56), a device with the InGaN layer removed in the access regions (only the InGaN film under the gate is left), and a conventional normally-on device (as in Fig. 5.56, but without the InGaN layer) [395]. A diffusion of the metal source and drain contacts reaching the highly-doped layer is assumed.

Figure 5.56: Schematic layer structure of the three HEMTs under investigation.
\includegraphics[width=14cm]{figures/sim/InGaN/Noff2.eps} Simulation Results

The simulation results for the transfer characteristics of the three devices are compared to the measurements of Mizutani et al. [394] in Fig. 5.57 for $ V_\ensuremath {\mathrm {DS}}$=5 V. Good overall agreement is achieved.

Figure 5.57: Comparison of simulated and measured transfer characteristics for the three devices.

All simulations were conducted using the same parameter setup, except for the work-function energy difference of the gate Schottky contact (depending on the underlying material). The values for the interface charge density are summarized in Table 5.3. A positive charge at the channel/supply layer interface is used, a negative charge between the supply layer and the passivation (in the case of D-mode and recessed E-mode), a negative charge between the InGaN cap layer and the AlGaN supply layer (both E-mode devices), and a positive between the InGaN cap layer and the passivation (E-mode non-recessed).

Table 5.3: Summary of values of interface charge density [cm$ ^{-2}$].
Interface D-mode E-mode Recessed E-mode
GaN/AlGaN 1$ \times $10$ ^{13}$ 1$ \times $10$ ^{13}$ 1$ \times $10$ ^{13}$
AlGaN/InGaN $ -$ -2.2$ \times $10$ ^{13}$ -2.2$ \times $10$ ^{13}$
InGaN/Passivation $ -$ 1.4$ \times $10$ ^{13}$ $ -$
AlGaN/Passivation -0.6$ \times $10$ ^{13}$ $ -$ -0.6$ \times $10$ ^{13}$

Fig. 5.58 shows the effective conduction band energies of D-mode and E-mode HEMTs at $ V_\ensuremath {\mathrm {GS}}$=0 V, $ V_\ensuremath {\mathrm {DS}}$=5 V in a vertical cut under the gate metal, as computed by the simulator. The band diagrams are shifted so that both Fermi levels are at 0 eV. Indeed, as suggested by Mizutani et al., a 2DEG channel is present in the D-mode device, while the negative piezoelectric charge at the InGaN/AlGaN interface raises the conduction band in the E-mode structure. Thus, the channel is depleted even at $ V_\ensuremath {\mathrm {GS}}$=0 V and the threshold voltage increases to positive values.

Figure 5.58: Energy band diagrams of a HEMT with (dot-dashed line) and without (solid line) InGaN layer.

Fig. 5.59 compares the simulated DC $ g_\ensuremath {\mathrm {m}}$ for the three structures. The drop in the measured $ g_\ensuremath {\mathrm {m}}$ at higher gate bias might be caused by non-idealities in the source and drain ohmic contacts, which are not considered in the simulation. A relatively good agreement between the simulated and measured output characteristics for a device with InGaN layer is achieved (Fig. 5.60).

Figure 5.59: Simulated DC $ g_\ensuremath {\mathrm {m}}$ for the three devices.

Figure 5.60: Output characteristics of a HEMT with non-recessed InGaN cap layer.

Small signal AC analysis using the calibrated setup delivers cut-off frequencies of $ f_\ensuremath {\mathrm {t}}$=7 GHz for the device featuring a complete InGaN layer and $ f_\ensuremath {\mathrm {t}}$=10 GHz for the recessed structure, respectively. The simulations suggest that reasonably higher values can be achieved by shorter gate lengths: e.g. peak $ f_\ensuremath {\mathrm {t}}$=30 GHz for $ L_{\mathrm{g}} =0.8 \mu\ensuremath{\mathrm{m}}$.

S. Vitanov: Simulation of High Electron Mobility Transistors