Iue Annual Review 2011

Biography:
Tibor Grasser was born in Vienna, Austria, in 1970. He received the Diplomingenieur degree in communications engineering, the PhD degree in technical sciences, and the venia docendi in microelectronics from the Technische Universität Wien, in 1995, 1999, and 2002, respectively. He is currently employed as an Associate Professor at the Institute for Microelectronics. Since 1997 he has headed the Minimos-NT development group, working on the successor to the highly successful MiniMOS program. He was a visiting research engineer for Hitachi Ltd., Tokyo, Japan, and for the Alpha Development Group, Compaq Computer Corporation, Shrewsbury, USA. In 2003 he was appointed head of the Christian Doppler Laboratory for TCAD in Microelectronics, an industry-funded research group embedded in the Institute for Microelectronics. His current scientific interests include circuit and device simulation, device modeling, and reliability issues.

Statistical Degradation of Nanoscaled Devices

The continuous downsizing of MOS transistors has lead to routinely available devices with dimensions in the deca-nanometer regime, for instance in SRAM cells. Conventional device reliability studies assume a certain defect density and describe degradation in a macroscopic manner. From that perspective, all devices fabricated in a well-controlled process will degrade in an identical manner. In contrast, however, nanoscaled devices will only have a small number of defects, each of which having a potentially much larger impact on the device behavior. For instance, in rare cases it has been observed that charge capture into a single defect can lead to device failure. In addition, even in a perfectly controlled process, the number of defects per device will be a stochastic variable. Also, the characteristic capture and emission times of the defects will be different for each defect. As a consequence, the degradation of each device can be radically different and it is no longer sufficient to study the degradation on a set of representative large-area devices. Instead, the distribution of device degradation has to be captured in order make reliable lifetime predictions. This distribution has been shown to be very wide, containing devices which do not degrade at all and those which fail after a single defect-activation event. Thus, rather than giving a single-valued lifetime, the lifetime becomes a stochastic quantity whose distribution needs to be understood.
As an example, the simulations shown in the Figure 1 and 2 demonstrate the variability of the lifetime due to the Negative Bias Temperature Instability (NBTI) for a device containing 12 defects. Given conventionally assumed densities, this corresponds to a 35nm x 35nm transistor. Even if the measurement could be repeated on the same transistor, the lifetime would be broadened due to the stochastic nature of charge capture (Figure 1). For the qualification of a technology, an even wider broadening is observed due to the wide distribution of time constants in the various transistors. This phenomenon will require a radical change in the qualification procedures.

Figure 1. Simulated repetitive degradation measurements on the same small area device containing 12 defects gives different results for each run, due to the stochastic nature of charge trapping (thin lines). As a consequence, the lifetime becomes a stochastic variable and is broadened by about one order of magnitude.

Figure 2. In order to qualify a technology, degradation measurements have to be repeated on different devices (thin lines). Since each small-area device will have a different number of defects with different time constants, an estimate for the lifetime can no longer be given without detailed knowledge of the distribution of the time constants.