Traditionally integrated circuits (IC) are manufactured by mounting a single die in a package. Thus, bigger dies in terms of space are needed to realize more complex circuits for a given technology node. This approach leads to a higher length of the interconnects. In contrast to the transistors the propagation velocity of interconnects did not increase by scaling, leading to higher signal run times. On the other hand more complex circuits can also be achieved through higher integration densities. This approach is restricted by limitations of the endurable power density. To avoid these circumstances three-dimensional (3D) integration was proposed  and is widely used for applications reaching from the miniaturization of portable devices to power efficient high performance computing, for instance servers and supercomputers . Thereby opportunities for improved power efficiency, increased band width, and lower latency can be harvested . This technology uses the third dimension by stacking the dies one above the other. With the introduction of this technology heterogeneous integration and smaller footprints became possible, leading to the opening of new product possibilities . In the process of designing 3D integrated circuits some factors, e.g. heat generation and dissipation, stress development due to the stacking, must be considered to avoid reliability issues and break down of systems .
For 3D integration not only planar interconnects, providing the connections of the devices on a single die, but also vertically connecting structures, applying the connections between the stacked dies, are required . These vertically connecting structures include solder bumps for the connections between the dies in contrast to a thinning and bonding process. Furthermore, through silicon vias (TSV) are used for the connection trough the dies. Due to the introduction of these components new reliability issues arise. These issues include delamination and cracking due to residual stress introduced from the fabrication process as well as thermal expansion  and void formation and growth because of electromigration (EM) [5, 72] among others [20, 24, 44]. Therefore, an adequate characterization of the vertically connecting structures is necessary to get a deeper insight of the failure mechanisms degrading these components.
The aim of this thesis is the implementation of EM degeneration models in the simulation tool COMSOL , based on the soft failure phase, and the EM assessment of the open TSV technology. Thereby the prediction of the lifetime of open TSVs and the localization of the areas with the highest failure occurrence probability are addressed. Furthermore, the results of simulations based on the finite elements method (FEM), taking all aspects regarding the two different phases of EM into account, are used for the calibration of a compact model.
Interconnect structures are responsible for the transmission of signals within electronic circuits. The first structures in use were single wire connections between the active, as electronic tubes and transistors, and passive elements like resistors, capacitors, and inductors found in old days radios. The next step was the development of printed circuit boards. These boards consist of copper layers laminated on polymeric substrates. By etching lithographically developed patterns into the copper, conductive tracks are obtained. This planar structure connecting the electric components exhibits low aspect ratios and allows the application of low cost wet etching techniques .
In integrated circuits the active components are placed in the substrate, usually silicon, whereon planar interconnect structures are grown. Besides the conducting lines several other layers are placed between them such as dielectric, etch stop, anti-reflective coating, diffusion barriers, and plugs realizing vertical connections, and thereby realizing multiple metallization layers .
The function of interconnection in integrated circuit is the distribution of the clock signals, the power, and the transmission of signals over the chip connecting various system functions. Due to the desired development of fast
integrated circuits the interconnects have to meet the high speed requirements for the clocks, the signals, as well as the down-scaling of sizes. A typical parameter for interconnect speed is the RC time delay given by the product of
the resistance and the capacitance of the line. To minimize this delay the interconnect structures have to be properly designed and material systems with conducting materials exhibiting low resistance as well as isolation materials
between the lines with low permittivity have to be developed and implemented .
The conducting materials should fulfill the following requirements:
high thermal conductivity
high melting temperature
compatibility to the isolation materials, the barrier, and capping layers
compatibility to the back-end-of-line process
The two materials primarily used for IC metallization are aluminium and copper. In Table 1.1 their most important material parameters are summarized.
|Specific e1ectrica1 resistivity ( cm)||2.72||1.71|
|Melting point (K)||933.5||1358|
Table 1.1.: Material properties of aluminium and copper .