PIC

DISSERTATION

Mechanical Reliability of Open Through Silicon Via Structures for Integrated Circuits

ausgeführt zum Zwecke der Erlangung des akademischen Grades
eines Doktors der technischen Wissenschaften

eingereicht an der Technischen Universität Wien
Fakultät für Elektrotechnik und Informationstechnik

von

Santo Papaleo Lange Gasse 24/17
1080 Wien, Österreich
Matr. Nr. 1329523
geboren am 11 August 1988 in Novara, Italien


Wien, im Dezember 2016

Ai miei Zii

Science is the belief in the ignorance of experts
Richard Feynman

   Kurzfassung
   Abstract
   Riassunto
   Acknowledgement
Contents
List of Abbreviations
List of Symbols
   Overview of Solid Mechanics and Finite Element Method
   Stress Evolution during 3D IC Stacking using Open TSVs
   Fracture Mechanics and Delamination in Open TSV
   Simulation of Intrinsic Stress Build-Up in Thin Metal Films
List of Figures
List of Tables
1 Introduction
 1.1 Integrated Circuits
 1.2 Interconnect Structures
 1.3 Through Silicon Vias
 1.4 Reliability of Interconnect Structures
 1.5 FEM Approach for Reliability
 1.6 Outline of the Thesis
2 Overview of Solid Mechanics and the Finite Element Method
 2.1 Continuum Mechanics
 2.2 Plane Strain and Plane Stress
 2.3 Source of Residual Stress in Thin Films
 2.4 Virtual Work
 2.5 Fracture Mechanics
 2.6 FEM
 2.7 FEM for Solid Mechanics
3 Stress Evolution during 3D IC Stacking using Open TSVs
 3.1 Stress Generation during 3D IC Stacking
 3.2 Nanoindentation
 3.3 FEM Approach
 3.4 Results and Discussions
 3.5 Summary
4 Fracture Mechanics and Delamination in Open TSVs
 4.1 Basis of Fracture Mechanics
 4.3 Energy Release Rate Calculation
 4.4 Delamination Prediction at TSV Bottom
 4.5 Experimental Analysis
 4.6 Comparison between J-Integral and
Regression Analysis

 4.7 Summary
5 Simulation of Intrinsic Stress Build-Up in Thin Metal Films
 5.1 Introduction
 5.2 Theoretical Background
 5.3 Volmer-Weber Model for Thin Films
 5.4 Results
 5.5 Summary
6 Summary and Outlook
A Kolosov-Muskhelishvili Formulas
 A.1 Airy Stress Function
 A.2 Analytic Function and Complex Variable
 A.3 Complex Representation of the Airy Stress Function
 A.4 Stress and Displacement described by
Airy Stress Function

B Westergaard Approach
Bibliography
Own Publications

Kurzfassung

Seit Kurzem hat die Halbleiterindustrie signifikante Anstrengungen in Richtung der Einführung von über Speicher und Logik Anwendungen hinausgehender zusätzlicher Funktionalität unternommen, welche auch als "More-than-Moore" Integration bekannt ist. Diese Art der Integration, allgemein mit drei dimensionaler Die/Halbleiterscheiben-Stapelung assoziiert, wird mittels Siliziumdurchkontaktierungstechnologie realisiert, welche eine vertikale, elektrische Kontaktierung zwischen Systemen erlaubt, geringen Energieverbrauch, dichte Bauteilpackung und reduzierte RC-Verzögerung ermóglicht. Die Implementierung und Fertigung dieser 3D Struckturen resultiert in vielen herausfordernden Zuverlässigkeitsproblemen. Daher muss die Zuverlässigkeit jeder Komponente des Gerätes sorgfältig analysiert werden. In dieser Arbeit wird die Zuverlässigkeit in Bezug auf die mechanische Stabilität von gefüllten (hohlen) TSVs basierend auf Wolfram-Metallisierung betrachtet. Die unterschiedlichen Aspekte welche die mechanische Stabilität von TSVs beeinflussen werden untersucht und neue Modelle implementiert.

Die Finite Elemente Methode (FEM) ist ein numerisches Verfahren das häufig in der Halbleitermodellierung zur Unterstützung der Entwicklung von neuen Beauteilen und Prozessen verwendet wird. Die mechanische Analyse der hohlen TSVs ist in einer kommerziellen FEM Software implementiert, welche unterschiedliche Schemata, Materialien und mechanische Modelle einsetzt.

Während des Stapelns von 3D integrierten Schaltungen können Bauteile wie die hohlen TSVs unbeabsichtigt externen Kräften ausgesetzt werden die zu einem Versagen der Strucktur führen. Durch die Simulation einer externen Kraft, die auf einen hohlen TSV wirkt, können kritische Areale identifiziert werden in denen ein mechanisches Versagen am wahrscheinlichsten ist. Die höchste Wahrscheinlichkeit eines Versagens durch Materialbruch oder Delamination ist an den Ecken des TSV-Bodens aufzufinden. Nachfolgend wurden die kritischen Areale lokalisiert und eine Delaminationsanalyse für die Materialgrenzflächen der Multilagenstrucktur am TSV-Boden durchgeführt. Die Delaminationsvorhersage wird durch die Energiefreisetzungsrate während der Delaminationspropagation beschrieben. Wenn die Energiefreisetzungsrate einen kritischen Wert überschreitet propagiert die Delamination. Bedingungen wie die Lagendicke, angewandte Kraft und der Reststress der involvierten Materiallagen werden variiert um zu untersuchen, welche Faktoren die Wahrscheinlichkeit einer Delaminationsfortpflanzung zu erhöhen. SiO2/W wurde als die kritischste Grenzfläche indentifiziert. Wenn für die Wolfram-Lage ein hoher Wert an intrinsischer Zugspannung angenommen wurde, wurden hohe Energiefreisetzungsraten erzielt.

Dünne Metallfilme, unter Verwendung von Complementary Metal-Oxide-Semiconductor (CMOS) Fertigungstechniken, enthalten für Gewöhnlich Reststress, der die Leistung und die Zuerlässigkeit von ICs beeinflusst. Hohe intrinsische Stresswerte, im Speziellen in der leitenden Wolfram Lage des offenen TSVs, erhöhen die Wahrscheinlichkeit eines delaminationsinduzierten Fehlers. Daher ist ein Modell zur Vorhersage des Stressaufbaus in dünnen Metallfilmen während des Abscheidungsprocesses implementiert worden. Das Model wird unter Verwendung von Messdaten für mehrere Materialen kalibriert und wird zur Untersuchung der Filmstressentwicklung während des Filmwachstums an einer ausgebogten Oberfläche verwendet. Während der TSV-Fabrikation bildet sich eine ausgebogte Oberfläche entlang der TSV-Seitenwand auf Grund des verwendeten reaktiven Ionentiefenätzprozesses. Dünnfilme die auf einer ausgebogten Oberfläche wachsen entwicklen im Vergleich zu ebenen Proben einen geringeren intrinsischen Stress. Daher kann der intrinsische Stress, durch die Kontrolle der Prozessparameter während des Ätzens, im Film minimiert werden.

Abstract

Recently, the semiconductor industry has been investing significant effort towards introducing more functionality to applications beyond memory and logic, referred to as “More-than-Moore” integration. This type of integration, commonly associated with three dimensional (3D) die/wafer stacking, is realized using a through-silicon via (TSV) technology, which allows for a vertical electrical contact between systems, enabling low power consumption, dense device packing, and reduced RC delays. The implementation and fabrication of the 3D structure results in many challenging reliability issues. Therefore, the reliability of every component of the device must be thoroughly analyzed. In this work the reliability related to the mechanical stability of lined (open) TSVs, based on the W metalization technology, is considered. The different aspects which impact the mechanical stability of the TSV interconnects are examined and new models are implemented.

The finite element method (FEM) is a numerical method frequently used in semiconductor modeling to support the development of new devices and processes. The mechanical analysis of open TSVs is implemented in a commercial FEM software, where different simulation schemes, materials, and mechanical models are employed.

During 3D integrated circuit (IC) stacking devices such as open TSVs can be subjected to unintentional extra forces leading to a failure of the structure. By simulating an external force acting on an open TSV critical areas can be identified, where a mechanical failure is most likely. The highest probability of a failure due to material cracking or delamination is found at the corner of the TSV bottom. Subsequently the critical areas are localized and a delamination analysis is performed for the material interfaces of the multilayer structure at the TSV bottom. Delamination prediction is formulated by using the energy release rate generated during delamination propagation. If the energy release rate exceeds a critical value delamination propagates. Conditions such as the thicknesses of the layers, applied forces, and residual stresses of the involved material layers are varied to investigate which factor increase the probability of delamination propagation. SiO2/W is found to be the most critical interface; when the W layer is assumed to carry a large value of intrinsic tensile stress, high values of energy release rate are obtained.

Thin metal films, deposited using complementary metal-oxide-semiconductor (CMOS) fabrication techniques, usually contain residual stresses, which affect the performance and reliability of the IC. High values of intrinsic stress, in particular in the W conducting layer of the open TSV, increase the probability of delamination-induced failure. Therefore, a model is implemented to predict the stress build-up in thin metal film during the deposition process. The model is calibrated by using measured data for several materials and is used to investigate the film stress evolution during film growth on a scalloped surface. During TSV fabrication, due to the deep reactive ion etching process used, a scalloped surface is formed along the TSV sidewall. Thin films grown on a scalloped surface develop a smaller intrinsic stress when compared to flat samples. Therefore, by controlling the process parameters during etching the intrinsic stress in the film can be minimized.

Riassunto

Recentemente, l’industria dei semiconduttori ha affrontato notevoli sforzi nell’introduzione di più funzionalità al di là di memorie e dispositivi logici. Questo approccio è chiamato “more than Mooore” integrazione. Questo tipo di integrazione, generalmente associata all’impilamento di die e wafer nelle tre dimensioni (3D), è realizzata usando la tecnologia di fori passanti su wafers di silicio (inglese Through Silicon Vias (TSVs)), che permette il collegamento elettrico verticale tra sistemi, permettendo bassi consumi energetici, densi imballaggi di dispositivi, e una riduzione del ritardo RC. L’implementazione e la fabbricazione di strutture tridimensionali hanno diversi importanti problemi di affidabilità da affrontare. L’affidabilità di ogni componente del dispositivo dev’essere dettagliatamente analizzata. In questo lavoro viene considerata l’affidabilità riguardante la stabilità meccanica di lined (open) TSVs, che utilizza come materiale conduttore il tungsteno. Vengono esaminati i diversi aspetti che impattano la stabilità meccanica di interconnessioni TSV e sono implementati nuovi modelli.

Il metodo ad elementi finiti (FEM) è un metodo numerico frequentemente utilizzato nella modellizzazione di semiconduttori; per descrivere, analizzare, e sviluppare nuovi dispositivi e processi. L’analisi meccanica di open TSVs è stata implementata con un software commerciale FEM, dove sono utilizzati differenti schemi di simulazione, materiali e modelli meccanici.

Durante l’impilamento di circuiti integrati nelle tre dimensioni, dispositivi elettronici come ad esempio open TSVs possono essere soggetti ad involontarie forze esterne portando al fallimento della struttura. Simulando una forza esterna agente su un open TSV, possono essere identificate delle aree critiche, in cui la possibilità che si verifichi un fallimento meccanico è molto alta. La più alta probabilità di fallimento a causa di rottura del materiale o delaminazione è stata trovata all’angolo inferiore del TSV. Successivamente aver localizzato le aree critiche, è stata svolta un’analisi sulla delaminazione per le interfacce presenti nel multistrato alla base del TSV. Le previsioni sulla delaminazione sono formulate utilizzando il tasso di rilascio d’energia generato durante la propagazione della delaminazione. Se il tasso di energia rilasciata supera un critico valore, la delaminazione propaga. Condizioni come lo spessore degli strati del materiale, forze applicate, e stress residui dei materiali utilizzati, sono stati variati per investigare i fattori responsabili dell’aumentano della probabilità di propagazione della delaminazione. SiO2/W si è rilevata l’interfaccia più critica; quando il tungsteno è ipotizzato con alti valori di stress interno di trazione, sono stati ottenuti alti valori di tasso di rilascio d’energia.

Strati metallici sottili, depositati usando le tecniche di fabbricazione complementary metal-oxide-semiconductor (CMOS), esibiscono stress residui, che influiscono sulle performance e l’affidabilità dei circuiti integrati. Alti valori di stress intrinseco, in particolare nel materiale tungsteno conduttore nelle open TSVs, aumentano la probabilità di fallimento dovuto alla delaminazione. È stato dunque implementato un modello che permette di simulare la formazione di stress intrinseco in film sottili durante i processi di deposizione. Il modello è calibrato usando dati sperimentali di diversi materiali ed è utilizzato per investigare l’evoluzione dello stress in film durante la crescita su una superficie ondulata. Durante il processo di produzione delle TSVs, vengono utilizzati processi di attacco chimico e lungo le pareti del TSV si forma una superficie ondulata. Gli strati sottili cresciuti su una superficie dalla forma ondulata sviluppano uno stress interno inferiore rispetto a crescite su campioni piatti. Per cui, controllando i parametri utilizzati durante l’attacco chimico lo stress interno dei film può essere minimizzato.

Acknowledgement

Firstly, I would like to express my gratitude to my supervisor Prof. Hajdin Ceric for the support of my Ph.D. study and related research. I’m very glad that he gave me the possibility to be part of his Christian Doppler Laboratory for Reliability Issues in Microelectronics.

I want, as well, to thank Prof. Siegfried Selberherr for his patience and help during my years at the institute.

I would like to thank Prof. Olivier Thomas that accepted to take part in the examining committee on such short notice.

Thanks to all the people of the Institute of Microelectronics. Thanks to them I had an enjoyable time at the institute.

Many thanks to Gerhard Rzepa, Wolfhard ZISSER, and Thomas Windbacher for translating the discussed abstract into German!

I am grateful to Raffaele Coppeta for having informed me about the Ph.D. position, honestly grazie, I will appreciate it forever!

I am very glad for having met the beautiful person of Thomas Windbacher, he gave me many suggestions about ALL kind of topics! Grazie bello!

I am really grateful to Lado Filipovic! Grazie and again grazie! I appreciated his patience and his accuracy. All his various suggestions, discussions, comments, and proofreading helped me a lot to improve my work. Grazie Lado!

Words cannot express my gratitude to Dipl.-Ing. Dr.Techn. Wolfhard ZISSER. I have found the many scientific discussions with him very important and fundamental. He has been my Austrian reference for any problem. Also I enjoyed our spare time at Karlsplatz, I will never forget these moments. Danke for having made my time in Austria easier and more enjoyable.

Furthermore, I had the good fortune to meet interesting people outside the institute. They gave me the possibility to fully experience the perfect and beautiful Vienna. I thank my initial flatmates, Marta and Renate, who warmly welcomed me and introduced me to Vienna, and I thank my current flatmates, Caroline and Venus, I had an enjoyable time in the flat with them. I thank Alessio, Arbi, Alberto, and Ornella, for helping me to survive in Vienna; I thank Giuseppe (small), Giuseppe (big), Gretel, Francesco (urologist), Malcolm, Marco (urologist), Paolo, and Valerio who have made me proud in these years to be an Italian abroad. All of them gave me the possibilities to rest and take a break from my studies, therefore thanks to all you.

Thanks to Micheal, Ilaria, Chino, Esther, Samy, Elisa, Simone, Nicola, and Cisco who encouraged me to take this adventure and later visited me in Vienna. Grazie amici!

I am thankful to Gino. He never complained or reproached my absence. Thanks puledro!

Starting this challenge in the first place was the “fault” of Marta C., Bobbio, and Benny who strongly pushed me. I express my deepest gratitude to them!

Many thanks to Marco and Silvia, sincere FRIENDS who have always been present in these years. I miss our time together in Lange Gasse and I am really sorry if I messed up your life!:) Thanks to them I will have beautiful memories of Vienna.

Thanks to Nino and Marianna. Grazie mille per avermi sempre incoraggiato, motivato, e spinto in questa esperienza. Avevate ragione in tutto, grazie!

I am really grateful to my parents, my sister and my grandmother. Grazie a mia mamma, che in questi tre anni mi ha sempre calorosamente cercato e riaccolto a casa come un re. Grazie a mio padre che mi ha sempre appoggiato, creduto e spinto nelle mie scelte. Grazie a mia sorella che mi ha fatto sempre sentire importante. Grazie a mia nonna, per avermi sempre dimostrato il suo affetto anche se siamo sempre stati distanti. Grazie per il vostro aiuto, se sono diventato quello che sono è stato solo grazie a voi. Ve ne sarò sempre grato.

As last, but not least, I want to thank Martina, my love. She never complained for the time that I did not dedicate to her, she rather always helped and encouraged me. I will be grateful to her forever. Abbiamo silenziosamente sofferto la distanza, ma forse (speriamo) è finalmente arrivato il tempo di stare insieme. Grazie per avermi aspettato per così tanto tempo.