(image) (image) [Previous] [Next]

Degradation of Electrical Parameters of Power Semiconductor Devices – Process Influences and Modeling

7.2 Hot carrier degradation

Hot carrier degradation (HCD), as described in Section 1.1.2, is the instability of a MOSFET due to large lateral electric fields during operation and the accompanying acceleration of carriers in the channel. To verify the impact of HCS on 4H-SiC-MOSFETs, test devices were subjected to large drain voltages and the change of the transfer characteristics or the CP current was investigated.

7.2.1 Bulk current

Previous work on HCD in SiC-MOSFETs [Ban+00; Yu+09] reported efficient photon emission at the drain side of the transistor indicating impact ionization of the energetic carriers. However, the impact ionization of carriers penetrating into the space charge region at the drain side can also be measured electrically on an nMOSFET via the substrate current [Sch06; BH10; OE10]. For illustration, the bulk current is measured as a function of (math image) for high drain bias as shown in Fig. 7.4.


Fig. 7.4: Drain and substrate current dependence on the gate voltage for large drain bias [Pob+14]. The substrate current measurements are labeled with the corresponding drain voltage.

Indeed, a bulk current is measured with a maximum at a certain gate voltage, which depends on the drain bias. The position of the maximum is \( \gls {Vg}=1/\alpha \times \gls {Vd} \) with \( \alpha =2\ldots 3 \). This is consistent with micrometer long Si MOSFETs which as well show a maximum at \( \gls {Vg}=1/\alpha \times \gls {Vd} \) [BH10]. The reason for the maximum is that the substrate current increases in the beginning with the gate voltage as an increasing number of carriers can reach the drain as the channel opens. For larger (math image) the device enters its linear mode and the lateral electric field decreases [Sch06]. The bias conditions where the maximum of the substrate current occurs is considered to be a bias point for efficient HCD. Consequently, the subsequent HCS phases are conducted at \( \gls {Vg}=\SI {25}{\volt } \) and \( \gls {Vd}=\SI {50}{\volt } \).

7.2.2 Stress impact

As shown in Fig. 7.5, the CP current increases considerably due to HCS.


Fig. 7.5: CP measurements before and after HCS of increasing duration [Pob+14].

The particular form of the stressed CP characteristics, especially the non-saturating behavior at high \( V_\tn {G,H} \), was attributed in Si devices to an increased number of border traps [Heh+09]. However, for SiC devices this increase indicates newly created interface traps because of an simultaneous large decrease of the drain current of the device, see Fig. 7.6.


Fig. 7.6: Change of the transfer characteristic with HCS on a linear (top) and logarithmic (bottom) scale.

The induced threshold voltage shift depends strongly on the readout bias, as shown in Fig. 7.7.


Fig. 7.7: Change of the transfer characteristic as a gate voltage dependent drift (bottom plot) with HCS [Pob+14].

From all these results follows that the high energetic carriers existent during HCS cause interface degradation.