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Degradation of Electrical Parameters of Power Semiconductor Devices – Process Influences and Modeling

2.3 Oxide field dependence

The oxide field for all devices was estimated by using the formulas presented in Fig. 2.1. The oxide field dependence is illustrated in Fig. 2.4 for the n \( ^{++} \)/pMOSFETs and in Fig. 2.5 for the p \( ^{++} \)/pMOSFETs, respectively.


Fig. 2.4: Oxide field dependence of the change of the CP current 41 ms after termination of a 100 s long stress at 50 °C for pMOSFETs with a n \( ^{++} \) doped poly gate [Pob+11a]. The different symbols correspond to three different devices with three different oxide thicknesses between 5.6 nm and 29 nm.


Fig. 2.5: The same as in Fig. 2.4 but for pMOSFETs with a p \( ^{++} \) doped poly gate. [Pob+11a]

For the n \( ^{++} \) poly gate devices both N- and PBTI show an equivalent behavior with a power law coefficient of about 4 which is close to the often reported value [Hua10; Gra+11c]. No visible influence of the gate oxide thickness is evident. For a stress and recovery temperature of 50 °C PBTI is more severe than NBTI.

For the p \( ^{++} \) poly gate pMOSFETs only NBTI has a comparable behavior and exhibits a power law coefficient of about 4. In contrast, the PBTI has a much lower power law coefficient of about 1.3. The different power law coefficient for PBTI suggests that it is not only the common N- or PBTI degradation mechanism which accounts for the degradation, but another mechanism might be involved. This becomes clearer in an investigation of the recovery behavior after stress.

In Fig. 2.6 the recovery of the CP current and the (math image) following PBTS is shown for thick oxide devices.


Fig. 2.6: Recovery after PBTS for thick oxide n- and pMOSFETs with either an n \( ^{++} \) doped poly gate or with n \( ^{++} \) or p \( ^{++} \) doped poly gate for either nMOSFETs or pMOSFETs, respectively [Pob+11a]. pMOSFETs do not show any drift in the (math image) regardless of the gate poly doping type.

As mentioned previously, PBTS causes a negative or a vanishingly small charge build-up close to the interface [Pob+11a]. Despite this, all devices experience about the same change in the CP current, but only the nMOSFETs, which is unfortunately only available with n \( ^{++} \) poly gate, experiences a drift in the threshold voltage. This shows that PBTS creates acceptor-like defects close to the interface which are either negatively charged or neutral depending on their charge state. Since the defects are all visible in the CP current but only for the nMOSFETs visible in the (math image) the energy level for the charge state transition must lie within the Si band gap, probably close to the intrinsic energy level (math image). Thus for thick oxide devices PBTS can create acceptor-like charges which affect the drain current only if the Fermi level is close to the conduction band edge, as it is the case for an nMOSFET during operation.

For devices with a thin oxide a build-up of positive charges after PBTS was observed. This is remarkable because the positive bias at the gate accumulates electrons at the interface and positive charge is in principle absent. The only region that contains a sufficient amount of holes is the p \( ^{++} \) doped poly gate at the other side of the oxide. This is because the high doping level of the gate poly of around 1019/cm3 inhibits its depletion. If the holes for the positive charge build-up during PBTS are indeed supplied by the poly gate, a positive charge build-up is supposed to be absent if the gate is replaced by n \( ^{++} \) doped poly. Unfortunately, no n \( ^{++} \)/pMOSFET with the thinnest 3.2 nm gate oxide is available. However, as mentioned previously, n- and pMOSFETs experience the same degradation except for a different Fermi level position during readout. Consequently, also a comparison with an n \( ^{++} \)/nMOSFET instead of a pMOSFET is possible. In Fig. 2.7 a comparison of the recovery behavior of those two devices after PBTS is shown.


Fig. 2.7: Recovery of the CP current and the threshold voltage shift in a thin oxide n \( ^{++} \)/nMOSFET and a thin oxide p \( ^{++} \)/pMOSFET after PBTS [Pob+11a]. The pMOSFET shows an NBTI-like recovery behavior after PBTS.

The p \( ^{++} \)/pMOSFET shows an NBTI-like recovery behavior meaning that positive charges are created during stress which recover subsequently after termination of stress. As suspected before, the n \( ^{++} \) gated nMOSFET shows indeed the creation and recovery of negatively charged defects. Thus a positive charge build-up after PBTS is only possible if the device has a p \( ^{++} \) doped poly gate and a sufficiently thin oxide such that the holes can tunnel from the gate towards the device into the defect [Pob+11a; Rot+12; TL+11a].

It is remarked that the finding that acceptor-like defects are created through PBTS is in contradiction to literature [Kat01; Den+04b; Gra+07]. A plausible cause for this contradiction is that these studies were performed on devices of CMOS technology. Other work on pMOSFETs with thick gate oxides [ZE98] still reported donor-like charges after PBTS. The results in [ZE98] are based on drain current–gate voltage (ID VG ) sweeps in the linear regime of the transistor before and after stress. However, in a repetition of the experiment a strong dependence of the \( \Delta \gls {Vg} \) on the voltage applied to the drain (math image), as illustrated in Fig. 2.8, was found [Pob+11a].


Fig. 2.8: Virgin transfer characteristics (upper plot) and drift versus gate voltage dependence after PBTS (lower plot) for two different drain voltages (math image) in the linear and in the saturation regime of the pMOSFET [Pob+11a].

In the linear regime of the transistor where \( \gls {Vd} < \gls {Vd}^\tn {sat} \), \( \Delta \gls {Vg} \) is largely negative above the threshold voltage of the device. It is remarked that the \( \Delta \gls {Vg} \) is measured with \( \gls {Vg} > \gls {Vth} \) in [ZE98]. This negative shift nearly vanishes provided the characteristic is measured in saturation, even though the (math image) should not affect the \( \Delta \gls {Vg} \) at all.

The strong difference in \( \Delta \gls {Vg} \) with different (math image) occurs because changes in the effective channel mobility (math image) have a different impact on the measured drain current from which the (math image) is calculated [Aic10]. A possible explanation is that the pinch-off effect in saturation reduces the channel length and thus decreases the impact of the channel mobility on the change of the drain current. This may be deduced from first order models for the drain current in the linear (lin) and saturation (sat) regime of a transistor [SN06]

(2.2–2.3) \{begin}{align} I_\tn {D}^\tn {lin} &= -\frac {W}{L} \mu C_\tn {ox} \left ( \gls {Vg}-\gls {Vth}-\frac {\gls {Vd}}{2} \right ) \gls {Vd}, \\ I_\tn {D}^\tn {sat} &= -\frac {1}{2} \frac
{W}{L} \mu C_\tn {ox} \left ( \gls {Vg}-\gls {Vth} \right )^2, \{end}{align}

where \( W \) is the channel width, \( L \) the channel length and \( C_\tn {ox} \) the oxide capacitance. From these equations it follows that changes in the drain current may be due to mobility changes or shifts of the (math image) as [Aic10]

(2.4–2.5) \{begin}{align} \frac { \Delta I_\tn {D}^\tn {lin} }{ I_\tn {D}^\tn {lin} } &= \frac { \Delta \mu }{ \mu } - \frac { \gls {dVth} }{ \gls {Vg} - \gls {Vth} - \gls {Vd}/2 } \\ \frac { \Delta
I_\tn {D}^\tn {sat} }{ I_\tn {D}^\tn {sat} } &= \frac { \Delta \mu }{ \mu } - \frac { 2 \gls {dVth} }{ \gls {Vg} - \gls {Vth} }. \{end}{align}

For a large overdrive, \( \gls {Vg}-\gls {Vth} \gg \gls {dVth} \), the change in effective channel mobility (math image) dominates the change of (math image). Operation of the transistor in the saturation regime increases the impact of the (math image) shift on the change of the drain current. In saturation the drift is roughly two times larger compared to the linear regime [Pob+11a].