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Degradation of Electrical Parameters of Power Semiconductor Devices – Process Influences and Modeling

1.2 Methods

The electrically observable result of a degradation mechanism like BTI is a change of the parameters of the transistor. Thereby, the threshold voltage (math image) and mobility of the MOSFET (math image) decrease. Usually, only the change of the threshold voltage is investigated since it is directly proportional to the number of charges created at the interface or within the oxide. If the charges are situated at the exact interface between the oxide and the semiconductor their number is straightforwardly calculated as

(1.1) \begin{equation} N = -\frac {C_\tn {ox} \gls {dVth}}{q}, \label {eq:NumberAndDrift} \end{equation}

where (math image) is the oxide capacitance per square centimeter and (math image) the elementary charge. A distribution of charges \( \rho (x) \) along the depth within the oxide \( x \), where \( x \) is zero at the gate-oxide interface and (math image) at the oxide-semiconductor interface, gives rise to a threshold voltage drift according to the Gauss law as [Seekn; Sch06]

(1.2) \begin{equation} \gls {dVth} = -\frac {1}{C_\tn {ox}} \frac {1}{\gls {dox}} \int _0^{\gls {dox}} x \rho (x) \tn {d}x.           \end{equation}

Due to the partial recovery of the charges created during BTS [Sch07], it is important to measure (math image) in a time-resolved manner after termination of stress.

1.2.1 Time-resolved (math image) measurements

Fig. 1.1 shows the concept of how the change of the threshold voltage is calculated from a change in the drain current [Kac+08].


Fig. 1.1: Schematics of the effective change of the drain current of a pMOSFET transistor with a shift of (math image). Neglecting transconductance changes a decrease of the drain current (math image) at constant gate bias (math image) can be mapped to a threshold voltage shift (math image).

This approach has several advantages:

  • • The measurement is a simple time-resolved current measurement for constant biases and can be performed usually on standard equipment with low experimental effort.

  • • Stress-induced degradation recovers quickly after a switch from stress to recovery bias. This raises the need to measure the drain current with a minimum delay after the gate voltage switch. With modern parameter analyzer equipment 100 µs to 10 ms delay times are possible. To further reduce the time to the first data point special setups using fast operational amplifiers are used [Rei+06]. The delay time of these setups is limited by the inverse of the maximum transfer frequency of the operational amplifier, which is approximately 1 µs. For even faster measurements the impedance of the gate of the transistor needs to be matched with the output impedance of the source measurement unit (SMU).

  • • Depending on the biasing of the MOSFET, the drain current is usually in the µA to mA range. Such currents can be measured with good accuracy. This leads to a very low noise level in the (math image) transients typically below 1 mV.

However, there are also several disadvantages connected with this method:

  • • The drain current depends on the mobility and on the threshold voltage of the device. Since BTI changes both parameters, the (math image) value calculated from (math image) is polluted with mobility changes. However, usually it is assumed that close to the threshold voltage of the device the impact of mobility changes is very small and can thus be neglected.

  • • The change in the drain current depends, to a small extend, on the supplied drain voltage. While it is important to keep the drain bias low during recovery to ensure symmetrical recovery conditions along the channel, a larger drain bias reduces the influence of mobility changes on the extracted (math image) value [Aic10].

  • • The recovery voltage after BTS must be in a range where the drain current is large enough to be measured. So in a simplified view, for an n-channel MOSFET (nMOSFET) only positive recovery voltages and for a pMOSFET only negative recovery voltages are possible, respectively. In particular, it is not possible to measure the recovery after BTS at the flat-band voltage, which would be very beneficial to determine the number of oxide charges created during stress. However, through a combination of measurements on nMOSFETs and pMOSFETs it is possible to acquire recovery data at arbitrary recovery voltages [ANG09b]. Also, the response at the threshold voltage following bias phases at arbitrary voltages can be studied [Gra+13a].

Despite these disadvantages, the measurement of the (math image) by recording the (math image) will be predominantly used throughout this thesis.

1.2.2 Charge pumping

Charge pumping (CP) is a measurement method where the gate voltage is periodically switched such that the MOSFET is brought from inversion to accumulation and vice versa. At every transition from the inversion to the accumulation phase a fraction of all charges remain in traps close to the interface due to finite trap emission time constants. In the subsequent accumulation phase these carriers are emitted and recombine with oppositely charged carriers of the body. This results in a current between the source-drain junctions and the bulk or body junction. This current is proportional to the density of traps with time constants smaller than about half of the inverse of the frequency [BJ69].

The commonly acknowledged model for CP is based on the Shockley–Read–Hall (SRH) theory [SR52; Hal52] for recombinations in semiconductors, which was extended for fast responding interface traps at the semiconductor-insulator interface [Gro+84]. The central result of the CP model is the equation

(1.3) \begin{equation} I_\tn {CP} = \gls {q} \gls {Dit} \gls {f} \gls {A} \gls {dEcp}, \end{equation}

where (math image) is the density of interface traps averaged across (math image), (math image) the frequency of the trapezoidal gate voltage signal, (math image) the area of the gate of the MOSFET and (math image) the energy range symmetrically around the middle of the band gap of the semiconductor. This energy is given by

(1.4) \begin{equation} \gls {dEcp} = 2 \gls {kB}\gls {T} \ln \left ( \gls {vth}\gls {ni} \sqrt {\sigma _\tn {n}\sigma _\tn {p}} \frac {|\gls {Vfb}-\gls {Vth}|}{\Delta \gls {Vg}} \sqrt {\gls {tf}\gls {tr}}
\right ), \label {eq:CPdEcp} \end{equation}

where (math image) is the thermal drift velocity, (math image) the intrinsic carrier density, \( \sigma _\tn {n} \) and \( \sigma _\tn {p} \) are the capture cross sections of an interface trap for electrons and holes, respectively, (math image) and (math image) are the flat-band and the threshold voltage of the device, respectively, \( \Delta \gls {Vg} \) is the voltage swing of the gate voltage signal and (math image) and (math image) are the falling and the rising times of the gate voltage signal, respectively.

The method is very precise, average interface trap densities down to about 109/(cm eV2) or even individual charges [SGD96] can be resolved.