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Degradation of Electrical Parameters of Power Semiconductor Devices – Process Influences and Modeling

Chapter 6 SiC-SiO2 interface characterization

In the following Chapter peculiarities regarding the characterization and degradation of SiC based MOSFETs are discussed. Peculiarities concerning the degradation of SiC-MOSFETs will be treated in Chapter 7. A few of the main differences between SiC and Si based MOSFETs are the occurrence of a virgin threshold voltage instability for SiC based MOSFETs [Gur+08] and the larger virgin trap density of SiC at the interface to the native oxide SiO2 [Afa+97; Cio05]. It is remarked that all subsequently presented measurements were performed on the four layer hexagonal SiC (4H-SiC) polytype.

The later in detail explained virgin threshold voltage shift is shown to be due to oxide traps and modeled using the analytical capture-emission time (CET) map model after [Gra+11a]. The model is shown to accurately predict the instability for a temperature range between room temperature and 200 °C, for positive gate voltages and in a time range from milliseconds to several days. The contents of that Section are also summarized in [PG13a].

The interface trap density of SiC based MOSFETs is determined by transferring the CP technique known from Si to SiC. Contrary to existing work regarding CP on SiC-MOSFETs [KTL96; SM98], it is shown that this characterization method can be used consistently and reliably on SiC, just as known from Si-MOSFETs.

6.1 Virgin threshold voltage instabilities

A simple turn-on of an SiC-MOSFET by simultaneously switching the gate and drain voltages to e.g. 15 V and 0.1 V, respectively, results in a continuous decrease of the drain current of the transistor. After this constant bias measurement an ID VG characteristic can be recorded which allows transforming the drain current change to a shift of the threshold voltage of the device [Kac+08] as shown in Fig. 6.1.


Fig. 6.1: Virgin drain current instability at a fixed operating point \( \gls {Vg}=\SI {15}{\volt } \), \( \gls {Vd}=\SI {0.1}{\volt } \) converted in an equivalent (math image) using a subsequently recorded ID VG [PG13a]. The measurement data is shifted along the y-axis such that the first measurement point is at 0 V.

Plotting this data on a logarithmic time axis reveals that the instability of the drain current does not saturate even after three days of constant biasing. The total change of the threshold voltage may be as large as 500 mV, which is small in comparison to the threshold voltage of about 15 V but still significant and undesirable for application purposes. If charging of the SiC-SiO2 interface or the oxide is the root cause of the instability then the decrease of the drain current can be due to either the creation of negative charges or the loss of positive charges. A reference which allows the identification of the charge polarity cannot be obtained since its measurement already changes the charge state of the MOSFET. Consequently, the first obtained measurement point must be defined as 0 V drift, even though the shape of the charging characteristic suggests that the device drifted already in the 10 ms before the first measurement point.

The instability is also visible in the ID VG curve of a virgin device by a comparison of two characteristics with different delays for each measurement point as shown in Fig. 6.2.


Fig. 6.2: Virgin transfer characteristic of \(100x2\) µm large SiC nMOSFET recorded with either 7 ms or 1 s delay between the bias switch and the current measurement (upper plot) and the according horizontal shift (lower plot).

The characteristic with longer measurement delay is shifted towards positive infinity with respect to the faster characteristic. This shows that already the measurement of a virgin ID VG is affected by the measurement timing. That is to say, SiC-MOSFETs do not exhibit a unique virgin transfer characteristic. This makes the characterization of SiC-MOSFETs more challenging.

The instability of the threshold voltage of SiC-MOSFETs is conventionally attributed to trapping of channel electrons (for nMOSFETs) into interface and/or oxide traps [Gur+08]. The effect was previously modeled using standard SRH theory [SR52; Hal52; Pot+07]. Negative charge build-up can only be due to either electron capture or hole emission. Within SRH theory, the former is independent of the position of the Fermi level because the emission time constants are described as

(6.1) \begin{equation} \gls {tau}_\tn {ep} \propto \exp \left (\frac {\gls {Et}-\gls {Ev}}{\gls {kB}\gls {T}}\right ) \end{equation}

with (math image) the trap level energy. That is to say, hole emission is not affected by a gate bias switch. In turn, electron capture time constants are modeled as

(6.2) \begin{equation} \gls {tau}_\tn {cn} = \frac {1}{ \gls {vth}[\hspace {-0.7pt}_{,n}] \gls {sigma}_n \gls {ni} } \exp \left ( \frac { \gls {Ec}-\gls {Ef}}{ \gls {kB}\gls {T}} \right ), \end{equation}

which means that a bias switch changes the capture times for electrons quasi-instantaneously. However, even if the Fermi level is pinned to the conduction band edge, which results in the smallest \( \gls {tau}_\tn {cn} \) values, one obtains 1017 s to 1022 s for typical values of \( \gls {vth}[\hspace {-0.7pt}_{,n}] \), \( \gls {sigma}_n \) and (math image). See Section 6.2 for a discussion on these material parameters. Accordingly, a distribution of electron capture time constants from 10−2 s to 105 s as shown in Fig. 6.1 cannot be explained with standard SRH theory.

Also, an adapted SRH model for oxide charges was tested which accounts for the depth \( x \) of the charge within the oxide by an exponential term as [Gra12, eq. (76)]

(6.3) \begin{equation} \gls {tau}_\tn {c} = \frac {\e ^{x/x_0}}{\gls {n}\gls {vth}\gls {sigma}_0} \label {eq:SRHoxideTrapsC} \end{equation}

for capture events and

(6.4) \begin{equation} \gls {tau}_\tn {e} = \frac {\e ^{x/x_0}}{\gls {Nc}\gls {vth}\gls {sigma}_0} \label {eq:SRHoxideTrapsE} \end{equation}

for emission events. Fig. 6.4 shows the resulting fit of this model to an interrupted MSM experiment. Consider Fig. 6.3 for the gate voltage sequence.


Fig. 6.3: Sequence of (math image) for the subsequent experiments. The time at the (math image) is multiplied by 10 after every break.


Fig. 6.4: Interrupted charging of an SiC nMOSFET with break time 1 s at room temperature and a comparison to the extended SRH model for oxide traps equation (6.3) and (6.4) [PG13a].

The model fails to explain the behavior of the SiC-nMOSFET because of the strong coupling of the capture and emission time constants resulting from the depth of the charge. Consequently, SRH-like models cannot describe the charging behavior of SiC-MOSFETs. This indicates that it is unlikely that the charges which cause the virgin threshold voltage instability are interface traps. More support for this argument is given subsequently.

6.1.1 Gate voltage influence

Before continuing with the analysis, the impact of the gate bias is analyzed. The choice of a particular gate voltage impacts not only the amount of (math image), as could be speculated from Fig. 6.2, but also the increase of (math image) per decade in time as shown in Fig. 6.5.


Fig. 6.5: Impact of the gate bias for the charging of a virgin device. The charging was interrupted at 1 s and 10 s after the beginning of the constant bias phase for a duration of 1 s. The ID VG is always recorded after the measurement of the drain current instability.

That is to say, the larger (math image) the larger the number of charges which can be activated with the constant bias phase. An intermediate bake steps of 10 s duration at approximately 130 °C with the poly-heater could be used to restore the virgin state of the device. Consequently, the experiments were conducted on the same device, even though the use of several virgin devices gives the same result (not shown). An analysis of the dependence of the drift after 100 s of charging in Fig. 6.6 shows a linear relationship between the (math image) and (math image).


Fig. 6.6: Dependence of the virgin threshold voltage drift on the gate bias. The result of a linear fit is given in the legend.

Also, applying a gate voltage sequence as sketched in Fig. 6.7 proves that different gate voltages give access to different defects [Lag+12].


Fig. 6.7: Sequence of the gate voltage for the experiment depicted in Fig. 6.8.


Fig. 6.8: Consecutive interrupted stress with different gate voltages. The sequence of the gate voltage is sketched in Fig. 6.7. All data is shifted on the vertical axis such that the first measurement point is at 0 mV.

Indeed, as shown in Fig. 6.8, independent energy regions are activated through different gate voltages. See also the sketch of the band diagram for this experiment in Fig. 6.9.


Fig. 6.9: Simple sketch of the band bending in the MOS system (upper plots) and the extension of the Fermi level into the oxide (lower plot) for different gate voltages.

To conclude, for a proper description an alternative model not based on SRH-like theories is needed. However, before discussing a possible physical origin of the instability, the problem is analyzed in a systematic way using CET maps [Rei+10; Gra+11a].

6.1.2 The CET map

A capture-emission time (CET) map is a two-dimensional plot of the density of traps versus their corresponding logarithmic capture and emission times [Rei+10]. For example, the CET map of the adapted SRH model is a narrow density parallel to the diagonal \( \gls {tau}_\tn {c}=\gls {tau}_\tn {e} \) because of the strong correlation of capture and emission times [Gra12, Fig. 47]. Integration of the CET map gives the number of trapped charges and thus the (math image) at arbitrary times. The integration area is defined through the duration of charging/discharging periods due to bias switches at the gate. The simplest case for charging traps in an SiC-MOSFET is to switch the gate bias from 0 V to the (math image) of the device as for the experiment shown in Fig. 6.1, which corresponds to a filling of the CET map from bottom to top. This typically results in a semi-logarithmic charging behavior [Oka+08b], which is due to a superposition of numerous individual charging events with a very broad distribution of capture time constants \( \gls {tau}_\tn {c} \) [Rei+10]. The energetic position of the traps responsible for the charging is between \( \gls {Ef}(\gls {Vg}=0\tn {V}) \) and \( \gls {Ef}(\gls {Vg}=\gls {Vth}) \). When the constant bias phase is interrupted, several defects emit their charge again, provided the interruption was longer than their emission time constants \( \gls {tau}_\tn {e} \). This leads to rather complicated charging transients like those shown in Fig. 6.10 and Fig. 6.11.


Fig. 6.10: Gate voltage sequence (top plot), CET map occupancies (middle plots) for (math image) phases of different length before a break and experimental result (bottom plot) [PG13a]. Longer charging phases before the break cause larger parts of the CET map to be occupied for the second charging phase. The red circles in the bottom plot indicate the theoretical merging points.


Fig. 6.11: Gate voltage sequence (top plot), CET map occupancies (middle plots) for varying duration breaks and experimental result (bottom plot) [PG13a]. The longer break phases remove a larger part of the previously charged parts of the CET map. All characteristic should theoretically merge at the same point in time with the continuous charging (no break) characteristic.

Independently of the exact distribution of \( \gls {tau}_\tn {c} \) and \( \gls {tau}_\tn {e} \), the transients of Fig. 6.10 and Fig. 6.11 can already be understood in terms of an occupation pattern in the CET map [PG13a].

6.1.3 CET map model

As seen before in Fig. 6.4, the experimental charging characteristic of an SiC-nMOSFET cannot be explained by an SRH-like model where the capture and emission time constants are strongly correlated. Also, the capture time constants are broadly distributed which causes the continuous charging characteristic shown in Fig. 6.1. This broad distribution of time constants makes a direct determination of the parameters of the distribution unfeasible because the tails of the distribution carry a lot of information. Therefore, an analytical ansatz following reference [Gra+11a] is validated against experimental data. The analytical model consists of two bivariate normal distributions of effective activation energies

(6.5) \begin{equation} E_\tn {A,c;e}=\gls {kB}\gls {T}\log \left (\gls {tau}_{c;e}/\gls {tau0}\right ) \end{equation}

for capture and emission time constants \( \gls {tau}_\tn {e} \) and \( \gls {tau}_\tn {c} \), respectively. Here, the scaling factor (math image) is an individual fitting variable for either bivariate normal distribution. The temperature activation is inherently considered since the distribution of activation energies instead of the time constants is directly fitted. The model has 12 parameters. For either bivariate distribution there are two values for the mean \( \mu _\tn {c} \) and \( \mu _\tn {e} \), two parameters for the variance \( \sigma _\tn {c} \) and \( \sigma _\tn {e} \) (the correlation is restricted and calculated from these two values as \( \rho = \sigma _\tn {c} / (\sqrt {\sigma _\tn {c}^2 + \sigma _\tn {e}^2}) \)), one minimum time constants (math image) and an amplitude giving the density of charges per eV2.

In a particular example, it was possible to fit one analytical model of two bivariate normal distributions to SiC-nMOSFET charging data measured at several temperatures between 30 °C and 200 °C. To illustrate this, Fig. 6.12 shows the result of the fit of the activation energy map shown in Fig. 6.13 to an example data set at 150 °C.


Fig. 6.12: Interrupted charging of an SiC-nMOSFET at 150 °C chuck temperature compared with the fitted analytical model after [Gra+11a] [PG13a].


Fig. 6.13: Example activation energy distribution for the interrupted charging shown in Fig. 6.12 [PG13a]. The green circles indicate the position of the experimental data used to fit the map. The color axis is normalized to display all details [Gra+11a].

The fitting result for other temperatures is equivalent. It is emphasized that this model accurately predicts the threshold voltage instability of this particular MOSFET within a few days and allows for accurate extrapolation to much longer times. This is true for temperatures of 30 °C to 200 °C and to gate voltages up to 25 V. That is to say, every charging/discharging pattern which might occur during operation of the device can be calculated with this model. This is especially beneficial for circuit designers who need to account for threshold voltage changes of a SiC-MOSFET in the design of the application circuit.