5.2 Single Electron Memories

  One of the major advantages of single-electron devices is their scalability down to atomic dimensions, which promises unprecedented integration densities up to 10¹⁰ gates, not just tunnel junctions, per square centimeter [9]. From an energy dissipation point of view, such dense structures are manageable, since in single-electron devices only few electrons are transferred through an extremely low capacitance system. From an interconnection point of view such small devices are questionable. Already today in CMOS technology at 0.25 $\mu$m do interconnect problems arise. How prominent must they be at structures ten or hundred times smaller. Single-electron memories are preferable, because due to their very symmetric structure, interconnect problems are lessened. Furthermore, bit-errors which can never be completely excluded are easier detectable and correctable in memory chips than in general logic circuits. These reasons let us believe that single-electron memories will be one of the first high volume applications of single-electron phenomena.

In the following a case study about single-electron memories is done to establish a better overview of their state-of-the-art. First we are going to discuss criteria which single-electron memories have to meet in order to be worth being considered for industrial mass production. Afterwards various memory designs are investigated and conclusions on their superiority or inferiority related to the demanded criteria will be stated. Many conclusions have been acquired from simulation results which were obtained with SIMON. SET memories should work at room temperature, 300 K, or at least at the temperature of liquid nitrogen, 77 K, with a reasonable bit-error rate. They should have as little power consumption as possible and at the same time should have short read and write cycles. Robustness against random background charge is a prerequisite, and the SET memory must be manufacturable with todays technology.