Erasmus Langer
Siegfried Selberherr
Abel Barrientos
Oskar Baumgartner
Hajdin Ceric
Johann Cervenka
Otmar Ertl
Lado Filipovic
Wolfgang Gös
Klaus-Tibor Grasser
Philipp Hehenberger
René Heinzl
Hans Kosina
Alexander Makarov
Goran Milovanovic
Mihail Nedjalkov
Neophytos Neophytou
Roberto Orio
Vassil Palankovski
Mahdi Pourfath
Karl Rupp
Franz Schanovsky
Zlatan Stanojevic
Ivan Starkov
Franz Stimpfl
Viktor Sverdlov
Stanislav Tyaginov
Stanislav Vitanov
Paul-Jürgen Wagner
Thomas Windbacher

Hajdin Ceric
Dipl.-Ing. Dr.techn.
ceric(!at)iue.tuwien.ac.at
Biography:
Hajdin Ceric was born in Sarajevo, Bosnia and Herzegovina, in 1970. He studied electrical engineering at the Electrotechnical Faculty of the University of Sarajevo and the Technische Universität Wien, where he received the degree of Diplomingenieur in 2000. In June 2000, he joined the Institute for Microelectronics, where he received the doctoral degree in technical sciences in 2005 and where he is currently employed as a post-doctoral researcher. His scientific interests include interconnect and process simulation.

Advanced Reliability TCAD with Atomistic Methods

In order to meet market requirements that behave according to Moore's law, physical scaling of circuit dimensions were employed in a traditional way to obtain commensurate performance gains. Performance has always improved primarily by shrinking the circuits, but there are obvious limits to this practice.
The total wiring length in state-of-the-art copper microprocessors spans several kilometers arranged in up to ten levels of wiring with hundreds of millions of interlevel connections. Competitive reliability targets for chip failure rates are in the order of one per thousand throughout the anticipated lifetime. This capability of producing even more complex wiring with equivalent or better reliability at chip level can only be achieved by understanding potential failure mechanisms and using this knowledge to select appropriate materials, optimize process procedures and controls, and apply design limitations. Our work focuses on the most urgent reliability issues of an interconnect/insulator system in a multilevel integrated circuit structure. The causes of material wearout and failure are either of electrical origin, like electromigration and time-dependent dielectric breakdown, or mechanical origin, like stressmigration, cracking, and delamination. For a very long time, macroscopic continuum models have sufficiently described these degradation phenomena. However, due to new technologies and ongoing miniaturization, material properties at the atomic level gain in importance. The local atomistic configurations of metals, metal/dielectric interfaces, and new low-k dielectrics often determine complex degradation processes that cannot be described by continuum models. The goal of our research is an integration of continuum based modeling with atomistic methods. Depending on specific problems and already established methods, this integration will follow different paths. One such path is to determine continuum model parameters by means of ab initio methods, while in other cases, results of atomistic level studies will lead to modifications and extensions of available macroscopic models. The application of atomistic methods are closely followed by a study of experimental data from the literature for the purpose of verification and calibration. The general usefulness of the newly developed methods and models are tested on the practical reliability problems from industry.


Variation of electromigration wind force on the copper surface.


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