The understanding and modeling of Hot Carrier (HC) degradation is one of the most crucial issues in the reliability of field effect transistors. The essential peculiarities of HC stressing are strong localization of the damage and less pronounced degradation at accelerated temperatures (opposite to Negative Bias Temperature Instability). Furthermore, the transformation of the output transistor characteristics during the stress is strongly dependent on the special location of the degradation portion and this position, in turn, is determined by the device architecture. Finally, as has been proved in the literature, HC degradation occurs even for extremely scaled devices where carriers in the channel cannot be treated as "hot", because they do not gain sufficiently high energy. Therefore, it is assumed that in this case the degradation is triggered by multi-particle processes. At the same time the degradation of long devices is dominated by single-carrier mechanisms. To summarize, HC degradation is controlled by carrier acceleration integral that accounts for carriers of all possible energies weighted with the cross-section of the process and with the probability of finding particles in the energy range. For assessment of such an integral, information about the distribution of particles over energies is necessary. Therefore, one should be able to calculate the Distribution Function (DF) of carriers concrete case, i.e. for concrete device architecture and given stress conditions. For this purpose, we use the full-band Monte-Carlo device simulator, which solves the Boltzmann transport equation by considering electron-phonon and electron-electron scatterings. Using this approach we analyzed two types of devices, namely, long channel low-voltage n-channel Metal-Oxide-Semiconductor Field Effect Transitor (MOSFET) of standard topology and high-voltage p-channel Laterally Diffused Metal-Oxide-Semiconductor (LDEMOS). We have shown that on these cases the HC degradation is dominated by a single-electron process, however, the multiple-particle contribution – even being small – is still pronounced and important. The worst-case condition for HC stressing are also analyzed well. We have demonstrated that simulations give the same result as experiment, i.e. for n-channel transistors, worst-case conditions are realized at Vgs = (0.4-0.5)Vds while for p-channel devices at Vgs = Vds.