List of Figures

• CIM, ECAD, and TCAD in VLSI manufacturing
• Nested VLSI design loops
• Local tool calibration
• Global tool calibration
• Inverse modeling of doping profile.
• Main GUI shell of VISTA/SFC.
• Communication between EVE interface, optimizer agent, and external optimizer.
• Simulation stages of TCAD analysis of integrated circuits.
• Applications and tools
• Data bypassing between subsequent tool calls
• Wafer model update by subsequent tool calls
• PIF objects in a PIF wafer state file
• GUI for viewing PIF data
• Data level integration schemes.
• Data flow for a consistent wafer model
• Selection of wafer state gridders: GUI module.
• Tool binding example code
• Input deck template example
• Template substitution statements examples.
• Graphical template editor
• Template editor in preview mode.
• Static calibration vs. matrix calibration.
• System tool encapsulation. Non-standard calling procedure.
• System tool encapsulation. Authorized execution hosts.
• Network data transfer synchronization shortcomings
• Fabrication of an integrated circuit from layout and process flow.
• Simulator-specific, process-specific, and equipment-specific statements.
• Mapping from process steps to tool steps
• Hierarchical process flow representation
• Object-oriented flow description interface
• Flow description ASCII representation
• Graphical flow editor for hierarchical flow definition
• Graphical tool selection interface for available simulators in VISTA/SFC.
• Wafer cross-section and lithography mask
• Generation of mask data from variational layout
• GUI for customizable project resources.
• Reduction of total computation by splitting
• Data sharing across splits.
• Data sharing between split branches
• GUI dialog for single-step operation.
• GUI for work-in-progress and status information for runs, system jobs, and hosts.
• Output data selection dialog
• 1-D plotting tool xpif1d
• VISTA/SFC as server in text-terminal mode
• Simple signal-based remote control mechanism
• Accessibility of orphaned runs
• Tasks, tools, and tool control level in VISTA/SFC.
• Design-space probing and simulation
• Layout parameter modifications cause topologically distinct wafer geometries.
• Process flow encapsulation with evaluable entity (EVE) objects.
• Examples of text-mode EVE commands
• EVE objects are combined to build complex tasks from simpler ones.
• EVE objects establish a uniform interface for evaluation requests by internal and external clients and applications.
• Text-mode commands for defining control variables in a flow EVE.
• Optimizer and RSM connected with EVE objects.
• EVE object manages evaluation instance (EVI) objects
• Optimization as minimization of target function.
• Calibration as minimization of the fit error.
• Calibration by transformation of input variables.
• EVE spreadsheet-GUI
• Graphical user interface for response surfaces
• Two-dimensional plot of response surface model.
• Final CMOS structure
• Net doping distribution in CMOS inverter
• Grid detail of N-device spacer region
• Short channel effect in NMOS transistor
• Simulation of nominal device
• Screening analysis for LAT implant
• RSM model generation and optimization statements
• p and n dopings without pocket implant
• p and n dopings with pocket implant.
• PIF Wafer Processor.
• Calibration pre-processor for PIF Wafer Processor.
• Value assignment in C and LISP
• Function declaration and definition in C and LISP
• LISP function header
• Callback concept for asynchronous communication between modules.
• Summary of PIF wafer information generated by pifmaid.