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2.9 Relevance of the hysteresis on normal device operation

The hysteresis effect discussed in this work is an outstanding difference between silicon and silicon carbide based MOSFETs. It is an intrinsic feature of MOSFETs based on wide bandgap semiconductor substrates. The reported hysteresis effect is visible on both investigated crystal faces and mainly present in the subthreshold regime, where the on-resistance (math image) of the device is still in the range of several megaohms. In saturation mode above threshold ( $\ac {vg}\geq \ac {Vth}$ , see inset in Fig. 2.1) the hysteresis vanishes. Consequently, the reported subthreshold hysteresis does not cause a dynamic change of during normal operation on a-face and Si-face devices and its impact on hard switching operation (e.g. switching very fast between accumulation and inversion) is negligible.

Figure 2.36: Drain current overshoot due to the hysteresis effect for switching gate bias with the high level close to (left) and higher (right). The overshoot of the drain current strongly depends on the minority carrier density in the channel and is therefore less important for typical operating conditions above (right).

(math image) — Figure 2.36: Drain current overshoot due to the hysteresis effect for switching gate bias with the high level close to (left) and higher (right). The overshoot of the drain current strongly depends on the minority carrier density in the channel and is therefore less important for typical operating conditions above (right).

It is important to emphasize that the reported hysteresis is not identical to classical BTI and cannot be considered as degradation. It is a fully reversible and reproducible effect which occurs on SiC-based MOSFETs and may have the following effects in the application:

(i) it may reduce switching losses because it actively supports turn-on and turn-off of the transistor due to the lower during turn-on and higher during turn-off.
(ii) it may cause a drain current overshoot when using fast switching slopes (high $\Delta V / \Delta t$ ). This overshoot is due to a temporary higher overdrive and a lower channel resistance at the very beginning of the high phase of the gate pulse.
(iii) a short accumulation pulse might lead to a leakage current at 0 V and increases the possibility of a parasitic turn-on due to the negative voltage shift.

According to available literature on the hysteresis [29, 43, 111], it has no negative effect on the performance and on the reliability of SiC MOSFETs. Nevertheless, it needs to be considered and understood in order to include the effect into circuit simulation and to correctly perform and assess threshold voltage measurements and BTI, as will be explained in Chapter 3.

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