As outlined in the previous section, characterizing oxide defects of scaled technologies requires testing many devices to obtain statistically significant results. In the previous section, this has been done by contacting and probing many individual devices using a semi-automatic probe station. However, handling such a system can be very error-prone as the positions of the needles can drift when many devices are contacted. This requires frequent manual readjustment, and thus makes the measurement of several hundreds of devices time-consuming and at some point unpractical. Here, a special array chip, purpose-built for this task, has been used instead. This approach allows for reliable and completely unattended measurements.
In this study, defects in high-k pMOS devices have been statistically characterized using a defect-centric approach. This has been done using array structures which contain thousands of nominally identical devices per device geometry. The defect-centric approach, as outlined in Section 3.3, has then been used to describe the statistical distribution of after stress over the full set of measured transistors. From this, the average number of defects remaining charged after stress, the average number of defects exhibiting RTN and the average step height of the defects could be extracted. The degradation measured on the devices has further been replicated using TCAD simulations to allow extrapolation of the degradation for lifetime estimation. Finally, the influence of bulk- and drain-bias applied during the stress phase has been investigated too.
The measurements have been performed on a custom designed chip which contains a matrix of MOSFETs of different geometries, as well as on-chip logic to select the individual devices. The selection logic is based on shift registers, which control double transmission gates on the gate and drain lines. The electrical layout of the matrix is shown in Figure 6.10.
As can be seen, the bulk and source connections are shared among all transistors, while the gate and drain lines are switched for the individual rows and columns of the matrix to select a single device for measurement. Rows and columns not selected are commonly connected and have been supplied by a gate-off and drain-off bias to assure a defined potential at their terminals. Additional information on the array chips can be found in .
This integrated device matrix allows to efficiently characterize many devices without user interaction. However, the matrix layout has the drawback that the leakage currents of all devices on the same drain line will contribute to the measured current. But this does not affect the extracted threshold voltage shifts, as these currents will contribute to both the initial () characteristics and the measured drain current traces, and thus cancel out during mapping of the device current to .
The array structures have been produced in a commercial, high-k/metal gate, planar technology. For each of the geometries available on the arrays, around 3000 devices can be addressed. For this study, pMOS transistors with gate widths of 100 nm and lengths of 30 nm and 150 nm have been used, henceforth called short and long devices, respectively.
All measurements have been performed using the same measurement sequence which has been repeated for each device characterized. The sequence consists of:
1. an initial () curve, used to determine the gate bias during the relaxation phases, and
2. eMSM measurements—as discussed in Section 4.1.3—with stress phases of
followed by relaxation phases of .
Recording of the recovery traces has been started 100 µs after stress release, with the sampling rate varied to achieve 200 samples per decade in time. In total 39 such sets of measurements have been recorded for the study, which resulted in more than half a million recovery traces. In addition to the two geometries, various combinations of gate, drain, and bulk stress biases have been investigated using these sets. All measurements have been performed at 35 °C using a custom-built defect probing instrument . In addition to the voltage sources for gate, drain and bulk, the transimpedance amplifier and the sampling unit for the source current as used in the previous section, the instrument was equipped with two additional voltage sources for the drain-off and gate-off biases, and electrically isolated IO-ports to control the on-chip logic of the arrays.
The gate-off and drain-off lines have been supplied with 0.15 V and 0.0 V, respectively. One set of initial () curves which have been recorded at the beginning of the measurement sequences is shown in Figure 6.11 for the long devices.
As can be seen, a significant variation of the threshold voltage of up to ≈30 mV compared to the average value can be observed at . After the measurements, these () curves have been used to map the drain current recorded during the relaxation phases of the eMSM measurements to . An exemplary set of () as has been mapped from the () recovery traces is shown in Figure 6.12.
From these recovery curves, distributions of have been drawn for the parameter extraction.
To check the function of the array and the device selection logic, and whether degradation is homogeneous over the area of the array, the degradation extracted after of stress at —the most severe stress condition applied—has been plotted over the array in Figure 6.13 (shown for the short geometry).
From the top plot, all rows and columns of the matrix can be observed to work properly, and no defective areas can be seen. The bottom plot shows the mean degradation for larger segments of the array. Again, no unexpected behavior can be observed, and degradation appears homogeneous over the entire area of the array.
The large number of recorded traces prohibits the usage of traditional methods for defect parameter extraction, like the ones outlined in Section 5.1. Instead, a statistical approach based on the defect centric model, as described in Section 3.3, has been used. From the measured threshold voltage shifts during relaxation, CDFs can be drawn for any moment in time. These CDFs can be reproduced using the defect-centric model with the equations given in Section 3.3. Examples of measured and calculated CDFs for one measurement set are shown in Figure 6.14. As can be seen, the model can accurately reproduce the measured distributions.
From the model, the average number of charged defects , the average number of active RTN defects , the average step height of a defect , and the parameters of the Gaussian measurement noise have been obtained. An overview of extracted parameters for the short devices is shown in Figure 6.15.
As expected, and remain constant throughout the measurement sets. The number of charged defects on the other hand strongly depends on the stress time and the applied gate and bulk biases. The dependence on gate bias and stress time is shown in Figure 6.16.
As can be seen, the number of defects charged during stress shows a strong increase both with gate bias and stress time, as expected for BTI. The average number of charged defects is low, with only around two defects per device for the most severe stress condition and down to 0.03 defects per device, i.e. one defect every 30 devices, for the weakest stress conditions.
A similar plot, which illustrates the relaxation behavior is shown in Figure 6.17. A relatively uniform recovery behavior can be observed along the logarithmic time axis.
To explain the device threshold degradation behavior and accurately identify the contributions of the many defects, the mean degradation measured at various gate stress biases has been replicated using TCAD simulation. For this, the open-source TCAD simulator Comphy  has been used. To calculate the behavior of the defects, this simulator employs an effective two state NMP model to mimic the charge transition kinetics of the defects, and their bias and temperature dependence. More details about this model can be found in Section 3.1.3. The defect bands used in the simulations have been taken from , where large devices of the same technology have been characterized and the respective simulation parameters have been extracted.
The results, shown in Figure 6.18, show good agreement between the measurements and simulations. For the combination of low stress times and gate biases, unusual negative shifts are experienced at very short recovery times. The origin of this behavior is currently unclear and requires further analysis.
Using the simulator, the stress and relaxation behavior shown in Figure 6.17 has been extrapolated to a ten-year time frame, which is a typical margin used in the semiconductor industry. The results are shown in Figure 6.19.
To investigate the influence of bulk and drain biases applied during stress on the device behavior, a number of measurement sequences have been recorded at or . In Figure 6.20, the average number of charged defects after of recovery are shown in dependence of . The measurements labeled with have been recorded with stress biases and , while the ones labeled with have been recorded with and . It can be seen that in both cases the degradation is governed by only.
In Figure 6.21, the device relaxation behavior is shown for the same cases. Measurements with pure gate stress are drawn using circles, while measurements with added bulk stress are drawn using crosses. Again, the experienced degradation and recovery seem dependent only on , independent of the potential applied at each contact.
However, this result is surprising, as the electric field in the oxide, which drives charge trapping, is largely determined by gate bias and the channel potential, which should be the source bias in inversion. While the gate bias may influence the density of carriers in the channel, the very similar influence of both gate and bulk bias may indicate insufficient control of the device channel during stress.
The dependence on drain bias stress is shown in Figure 6.22. The results do not show any significant influence of the mild drain stress applied. This seems reasonable, as the applied drain stress is well below the hot-carrier regime.
The custom test chip used in this study allows to efficiently record sufficient statistics for single device characterization and statistical evaluation of the device performance degradation. With this setup, over half a million relaxation traces could be recorded at various stress cases. To analyze this large amount of data, the defect centric model has been used. From this, the behavior of the devices in dependence of gate, bulk, and drain stress, as well as stress time has been investigated. Both gate and bulk stress parameters have severely affected the measured BTI in these devices, consistent with  while the elevated drain bias had no effect. The average step heights as well as RTN activity have been independent of the stress parameters. Simulations using defect bands from literature measured on larger devices of the same technology agree with the measured data and allow for lifetime extrapolation employing the measurement data at hand.