Electrically active defects are inevitably introduced or created during manufacturing of semiconductor devices. Even worse is the fact that such defects can also become newly created during operation at nominal bias conditions. Thus the understanding of the behavior of the defects and their impact on the device performance is essential for further optimization of the MOS transistors. The physical nature of these defects ranges from contaminating foreign atoms in the material or on surfaces to unsatisfied chemical bonds at material interfaces or even stretched bonds in an amorphous oxide. The defects either carry a fixed electrical charge or posses the ability to capture electrical charge during operation. Their presence negatively affects the operation of the device, and may lead to gradual or instant failure of the device if there is too many of them. While advantages in the manufacturing of devices have considerably reduced the number of defects found in mature technologies, a significant number of defects are still prevalent and require accurate physical description to estimate the device lifetime and yield for various operating conditions. For this, suitable defect models are typically calibrated to experimental data.
In the following chapter, an overview of the defect types and candidates which are considered in this work is given. The chapter is split into three sections, devoted to interface-, oxide-, and bulk defects. Agents of each of the defect categories exist in a different electrical and structural environment, hence their physical nature, as well as their impact on the device and the reliability issues they ultimately cause differ. Discussion of the defect classes is aided by the available knowledge on defects in the Si/SiOmaterial system, which is—due to its technological relevance—the best studied material system in semiconductor physics.
During device manufacturing, in particular when growing or depositing the insulating layer on top of the semiconductor substrate, the structural mismatch between those materials usually results in defects in the interfacial layer between them. The density of these defects is strongly dependent on the semiconductor and insulator materials used, the processing parameters and other species available during processing, which may passivate these bonds. Control of interface defects is one of the main technological challenges faced when introducing a novel material system. For example, in-situ oxidation and hydrogen passivation has led to a very low achievable interface defect density in silicon devices on the order of 1010/(cm2 eV) . This is together with the high quality of the oxide one of the main reasons why the Si/SiOmaterial system still remains the most successful technology today.
To study interface defects in silicon MOSFETs, ESR measurements have been performed in the 1960s. One of the earliest studies was carried out by Nishi et al. , where three distinct defect signatures were found on (111) interfaces. The P centers they identified can be found on (110) and (100) oriented surfaces as well [34, 35]. In addition to the original P center (), which is now widely known as P center in the context of (110) surfaces, chemically different P centers were found on (100) oriented Si interfaces, which are suspected to be oxidized P centers, i.e. . An illustration of these defects is shown in Figure 2.1. These so-called “dangling bond” defects involve unpaired bonds located at silicon atoms. P centers have two trap levels in the silicon band gap , one above mid-gap where they can trap an extra electron and one below mid-gap where they can emit their electron—this property of the defects is called amphoteric. Due to their location in the device, interface defects exchange charge primarily with the semiconductor substrate. Compared to other defects, interface defects act as fast traps, as they are close to the substrate valence and conduction bands, which act as charge reservoirs, and their relaxation energies are low.
The main issue with large densities of interface defects is the decreased controllability of the carrier density in the channel. This is due to trapped charges at interface defects counteracting the charge accumulating at the gate. In addition to this, interface defects increase noise in the channel current due to RTN and decrease the channel mobility. Their number may increase with hot carrier stress due to depassivation, which can lead to long-term degradation of device parameters.
Aside from ESR measurements mentioned above, further methods of interface defect characterization include capacitance-voltage (CV) measurements, charge pumping (CP) measurements, deep-level transient spectroscopy (DLTS) and direct-current current-voltage (DCIV) measurements, which are discussed in Chapter 4. All these methods have in common that they cannot study the impact of individual interface states on the device behavior, but record average properties of the defects.