Defects play a substantial role in semiconductor devices. They impact the feasibility of devices made from novel materials as well as the reliable and failure-safe operation of devices manufactured in mature technologies. Hence, it is no surprise that numerous methods have been developed over the last decades devoted to characterization of their physical nature.
In this chapter, methods used for experimental defect characterization will be discussed. The main focus of this chapter will be placed on electrical methods which have been implemented or employed by the author during his PhD studies. The discussion of these methods will also include details on the capabilities required of the measurement equipment. The chapter is split into three sections. In Section 4.1, electrical characterization methods which derive information on the device performance from the channel current in MOSFETs. This includes RTN, BTI/TDDS, and () measurements. Section 4.2 will discuss electrical methods which measure defect charging currents in MOS capacitor (MOSCAP) or MOSFET structures, e.g. capacitance-voltage (CV), charge pumping (CP), deep-level transient spectroscopy (DLTS), direct-current current-voltage (DCIV), and thermal dielectric relaxation current (TDRC) measurements. Finally, in Section 4.3, physical methods which do not involve direct measurement of device currents are discussed.
As described in Chapter 2, charged defects located spatially in between the gate and the conducting channel influence the electrostatics of the channel in inversion. This is due to Coulomb interaction between the trapped charge and the channel carriers, which in the most common case effectively lowers the carrier density in the vicinity of the defect. The impact of a defect on the channel current depends on the resulting perturbation of the current percolation path . This affects the drain-source conductivity which can be measured and employed for defect characterization. In this chapter characterization methods based on this effect are discussed. The fact that the influence of such defects increases with device scaling also enables the possibility to observe charge transitions of single defects in these measurements, given the gate area is small enough. Unlike for other methods discussed in this chapter, full MOSFET structures are required for all methods presented here.
The measurements used to observe changes in the channel conductivity rely on recording the drain-source current at constant drain-source bias and device temperature. Two distinct measurement schemes exist for this type of characterization . In the more popular constant-voltage measurement scheme, both the drain-source bias and the gate bias of the DUT are controlled externally, while the drain or source current is converted to a voltage and subsequently measured by an additional digital-to-analog coverter (DAC), see Figure 4.1. In contrast, the constant-current scheme aims at controlling the drain-source bias directly, while the gate voltage is controlled via a feedback loop of an operational amplifier, see Figure 4.2. The control input for the feedback loop is a second external voltage which defines the drain or source current of the DUT. The gate voltage applied via the feedback loop is measured directly by an ADC or an external device like an oscilloscope. The decision which method should preferably be used is difficult: The constant-voltage scheme has the benefit of simplicity but the drawback is that to obtain the threshold voltage shift the obtained current has to be mapped with a pre-recorded () curve. However, the characteristic of the () can alter during the measurement, i.e. not only the threshold voltage but also the sub-threshold slope can change, which cannot be considered when mapping the current to . The constant-current scheme may seem more suited in this case, but due to the feedback loop formed by the DUT and the OPAMP, it is more challenging to implement as the stability of the feedback signal has to be ensured.
The circuits which have been used in practice, however, incorporate a number of additional components. To switch between multiple amplification ranges, relays may be added which enable utilization of different resistor values. Additional passives may further be included to either improve noise figures by limiting the frequency range, or for circuit stability in case of the constant-current scheme. In addition, one might also want to measure the gate current to characterize SILCs.
Possible choices for control and measurement devices may be any combination of custom built voltage sources and sampling circuits, commercial source units or digital storage oscilloscopes. However, the control of the timing of the experiments and also achieving the highest SNR remains a formidable challenge for developing of measurement tools in general.
The measurement system which has been used by the author for the characterization methods outlined in this chapter is a custom designed, modular system, specifically developed for defect characterization. The reasons for using a custom system is in the requirements that come with TDDS and RTN measurements, which require long recording times at relatively high sampling rates, accurate synchronization between the outputs and inputs, as well as a high resolution of the recorded current signals. Part of the work of the author during his PhD studies was in developing this system and advancing its capabilities.
The current version of the system is based on a 19" rack case with slots for 12 inserts. Inserts can be equipped from the front and connect to the case via back-panel connectors. Slots one and two of the system are occupied with a power supply unit for the analog and digital circuits. The back-panel supplies the remaining slots with the analog and digital power and individual universal serial bus (USB) connections which terminate at a USB hub in the back of the case to interface the units to a measurement PC for control and data transmission. In addition, the back-panel offers an inter-integrated circuit (IC) bus for communication between the units and signaling lines such as a sampling clock and a trigger line to synchronize the measurement outputs and inputs. In the minimal configuration for measurements of the channel current of a MOSFET, one of each of the following units has to be equipped as shown in Figure 4.3:
• Control unit: A purely digital insert which controls measurement clock, trigger and abort lines, and additionally supplies digital IO signals via a front-panel connector, e.g for the control of array chips (see Section 6.2) or other periphery.
• Voltage unit: Supplies three separate analog signals . The signal output can be synced to the sampling unit(s) and switched at defined points in time between phases of the measurement, e.g. for BTI measurements. User defined ramps and arbitrary signal output is possible up to a frequency of 2 MHz, the signals are loaded via USB and stored in the connected RAM. Variants with different voltage ranges are available.
• Source measure unit (SMU): Contains a transimpedance amplifier stage as shown in Figure 4.1 which mirrors the voltage on terminal on terminal while at the same time measuring the current on this terminal. The current is translated to a proportional voltage and optionally DC-filtered, post-amplified, or attenuated before being output on . Multiple measurement ranges are available for selection.
• Sampling unit: An insert which samples a voltage at a frequency of up to 2 MHz with 18 bit resolution. It may be used in conjunction with the source-measure unit to measure a current or on its own to measure a voltage, e.g. for CV measurements. The analog input can be DC-filtered and pre-amplified or attenuated before sampling. Sampled data can optionally be averaged using an averaging table to reduce the effective sampling rate and improve noise, or to achieve logarithmically increasing time steps. Finally they are stored in RAM before being transmitted to the measurement PC via USB.
Possible configurations for measuring the channel current of a MOSFET at its source or drain terminals are shown in the lower part of Figure 4.3. The measurements are controlled from the PC using a python framework which allows the user to configure and run measurements. After completion, the framework receives the acquired data, corrects them using calibration values stored in the respective units, calculates the current values from the sampled voltages using the values from the trans-impedance amplifier and writes the data in a file.
The flexibility this system offers allows to configure it for many characterization methods, including RTN, BTI, TDDS, on-the-fly (OTF), and current-voltage (IV) / hysteresis measurements as outlined in this section or CV, CP and DLTS measurements as shown in the following section. The gate current can be recorded alongside the drain or source current by adding a second set of SMU and sampling units.
RTN describes an effect which causes noise in the drain-source current of MOSFETs. It is caused by individual oxide defects stochastically charging and discharging during device operation. Noise in MOS transistors typically shows a 1/f spectral behavior, also known as pink noise or flicker noise. McWorther first proposed that this phenomenon originates from individual defects dynamically charging and discharging during device operation . It has been further observed that the measured noise power scales roughly inversely proportional to the gate area of the devices . As the feature size of MOSFETs decreased, Ralls et al. were able to measure discrete steps in the channel current, and thus show that the observed 1/f noise can be linked to individual defects which modulate the resistance of the inversion channel . This effect paved the way for the observation of the behavior of individual defects when measured on small gate area devices.
The characterization of RTN appears—in terms of the measurement requirements—as one of the most straight-forward methods for defect characterization. The whole measurement procedure consists of applying defined bias voltages and recording the drain or source current. A common measurement scheme performed on small devices is to record the drain current over time at multiple gate voltages to obtain the bias dependence of the charge transition times of single defects. On large area devices, where only the superposition of the contribution of many individual defects can be studied, the main interest is the noise amplitude or power, which may also be recorded for a range of voltages. For the bias selection, typically a small drain-source voltage—usually on the order of 100 mV for nMOS/pMOS devices—is chosen, sufficiently large to measure the channel current but low enough not to cause any hot carrier related effects. The gate bias is often varied in the sub-threshold to threshold region.
Typical measurement results are depicted in Figure 4.4. For large area devices, typically a signal containing 1/f noise is obtained, while for small area device, individual steps are visible. The spectra of each contribution of an individual defect can be described by a Lorentzian PSD, which shows a plateau below a certain frequency and decreases proportional to above that. For many defects with border frequencies spread equidistant over the logarithmic frequency axis, this adds up to a 1/f PSD, as can be observed for large area devices.
To show the relation between 1/f noise in large area devices and RTN in small devices, we start with the Lorentzian PSD of a two-state RTN signal, as shown in Figure 4.4. It can be calculated using the Wiener-Khintchine theorem from the auto-correlation function of the RTN signal [89, 90]:
Here, is the step height, and is the mean frequency of the noise signal. For a number of defects, the spectral density is given by a superposition of the individual Lorentzian spectra:
In large gate area transistors there is a large number of defects present with an apparently uniform distribution of . Equation (4.2) can be simplified by condensing all defects with similar corner frequencies. For this, all defects within a small range are substituted with a defect with and an equivalent step height , which simplifies the expression for the PSD to:
In Equation (4.3), one term of the sum will be dominating at any frequency due to the characteristic shape of the Lorentzian PSDs. The maximum of the inner function is at , thus the dominating term is the one with its corner frequency at . By considering only the dominant defects, Equation (4.3) simplifies to
While this approximation is rather crude, it shows the link between RTN and 1/f noise. This also underlines the fact that characterization of RTN data is possible both in time- and frequency-domain. In this work, I will focus mostly on characterization of time domain data, as this enables a more direct observation of the behavior of individual defects.
The defects which may be characterized by RTN are those which are located energetically close to the Fermi level of the channel or the gate at the applied measurement conditions, as shown in Figure 4.5. The occupancy of such defects will be significantly larger than zero and smaller than unity, which causes these defects to stochastically change their charge state within a reasonable measurement time window. By modifying the gate bias, the area in the band diagram which is scanned can be changed.
The energy range which can be characterized depends on the maximum ratio between the transition times which can be extracted from the measured data and the temperature. From Fermi statistics it follows that
For example, at a given maximum ratio of measurable transition times and , , which means that in this case defects located in the range 120 mV above and below the Fermi level can be characterized.
Due to the stochastic nature of the capture and emission events, the actual characterization range for single defects is smaller than the previously estimated measurement window spanned by the sampling time and the measurement length. This is both due to the statistical variation of the dwelling times of a certain defect, as well as due to the requirement to measure multiple capture and emission cycles to accurately extract the average times. To predict the error due to a limited number of observations, the chi-square distribution can be used. It estimates the relative one-sigma confidence limits for the charge transition times . For more than a handful of transition events observed, the width of the Gaussian distribution is close to the chi-square distribution and might be used instead to approximate the error as , with the number of observations . From this, one can see that to achieve a reasonable error margin of approximately 10 %, 100 transition times have to be averaged. With only 10 observations, the error is still at approximately 30 %.
Finally, the measurement window is further reduced by the fact that the lowest dwelling times should be at least a few sampling times long. As the single defects are assumed memoryless, i.e. their statistical properties do not depend on their history, their transition rates are constant as long as the system is in equilibrium. This results in exponential distributions of their capture and emission times. The quantile function of the exponential distribution is , with the quantile . This gives and for the 0.01 and 0.99 quantile, respectively. Thus, in practical terms the measurement window is nearly two orders of magnitude smaller than the scanning range at both the top and the bottom . This requires a large sampling buffer length in excess of 100 kS to scan for defects. If only specific defects are to be analyzed, shorter sampling buffers might be possible.
Parameter Extraction The parameters of the RTN signals prevalent in the single defect measurements are the average charge capture and emission times, and the step height of each defect. A number of methods have been developed for extracting these parameters for the defects observed in such a measurement. They will be discussed in detail in Section 5.1. Once the characteristic parameters of an individual defect have been obtained at a number of measurement conditions, e.g. at different gate biases and device temperatures, they may be evaluated by comparison with TCAD simulation as outlined in Section 3.2. This finally yields the parameters of the employed defect model (see Section 3.1), such as the defect energy, position and curvatures of the parabolas. Alternatively to typically computational expensive TCAD simulations, an analytical method can be used to estimate the trap level and vertical position of a defect from the transition times, given in Section 5.1.4. However, the parameters of this method are often not very accurate. The results from this method may also be used as an initial guess for TCAD simulation. A flowchart illustrating the process is shown in Figure 4.6.
So far the main focus has been put on noise in the drain-source current, but also the gate current can show noise similar to the one observed in the channel current. This may be aided by defects which assist tunneling of carriers between the gate and the channel. Recently, it was shown [93, 94] that there is indeed correlation between discrete gate and drain current noise. However, the reports available from literature are quite contradictory. While charge transitions are observed which lead to an increase of both the gate and the drain current, the opposite behavior is also observed. This opposite effect seems to stem from the inhibition of direct tunneling between the gate and the channel by charged oxide defects . Additionally, SILC gives rise for an increase of the noise in the gate current as more defects get activated and created which can interact with the gate. Although the noise of the drain-source current is currently the primary subject of most RTN studies, the evaluation of the gate current is of equal importance and may provide missing information to the physical understanding of charge trapping in MOS devices.
A common way to learn about the reliability of a technology is to subject devices to stress conditions fairly exceeding the nominal operating range, in order to accelerate degradation mechanisms and allow for observations within a reasonable time window. This can include elevated gate and/or drain biases, device temperature or exposure to light or ionizing radiation. The basic measure stress measure (MSM) scheme consists—as the name suggests—of three phases. First, a measurement of a virgin device is taken. This is followed by the application of defined stress conditions, and finally another measurement. The original measurement can then be compared to the post stress measurement to evaluate the effect of stress. The stress and measurement part may be repeated multiple times, commonly with harshening stress conditions. An illustration of this scheme is given in Figure 4.7. In the example, the device is subjected to gate bias stress, and in the measurement phases () curves are recorded. Apart form IV measurements, this basic scheme is also used with e.g. CV and CP measurements.
The transfer characteristics () is one of the most important characteristics of the MOSFET. By comparing () characteristics of devices before and after stress, the threshold voltage shift, and changes of the sub-threshold slope, the mobility and the on and off current can be obtained, as illustrated in Figure 4.8.
In addition to the information that can be obtained by comparing a device before and after stress, further information can be gained by observing the behavior of the device after stress release. In the extended MSM (eMSM) scheme , phases of stress are alternated with measurement phases at recovery conditions as shown in Figure 4.9. This is of particular interest if the effect of stress is—at least in part—reversible, as is the case for BTI stress.
In large devices, eMSM measurments are often used to characterize the effect of BTI or HC stress. To measure BTI stress using the eMSM scheme, the drain and gate terminals of the device are kept at ground while a gate bias at or above the threshold voltage is applied during the stress phase. During the relaxation or recovery phase, the gate bias is set to a lower readout value while a small drain bias—commonly 50 mV or 100 mV for Si technology—is applied in order to ensure a small channel current. By using an initial () measurement recorded before stress, the temporal behavior of the channel current can be mapped to a threshold voltage shift during relaxation. After the recovery phase, another stress phase may be performed and the recovery behavior monitored afterwards. Subsequent stress phases are often chosen with increasing stress times, as shown in Figure 4.10. The corresponding recovery phases are usually chosen long enough that most of the recoverable part of the degradation vanishes. As the recovery times used for MSM sequences are very long compared to noise measurements, sampling is usually performed at logarithmic time instances for this type of measurement in order to keep the amount of samples feasible.
Hot carrier stress can be characterized in a similar manner, but with different bias conditions applied during stress. For HC stress, the gate bias applied is commonly chosen lower than for BTI but a significant drain bias, often larger than the gate bias, is applied. The drain bias which causes the most severe degradation depends on the geometry of the device and ranges from to . The drain-source voltage causes inversion layer charges to gain energy by accelerating towards the gate. The hot carriers may then either damage the interface directly or generate other hot carriers as shown in Figure 4.11.
Another application which makes use of eMSM measurements is TDDS. More precisely, the TDDS aims at the characterization of single defects. On small gate area devices, as described in Section 4.1.1, charging and discharging of such defects can be observed within the relaxation traces. This can be used in conjunction with BTI or HC measurements to characterize their charge trapping kinetics at various biases and temperatures in order to develop a physical explanation for their behavior.
Measurement The measurement conditions for TDDS are the same as those used for BTI or HC measurements on large devices. The difference is that each stress condition is measured multiple times to gain sufficient statistics on the capture probabilities and emission times of the single defects, as outlined for RTN single defect measurements (Section 4.1.1). The characterization windows for TDDS measurements are determined by the charge capture time during stress and the charge emission time during relaxation of the respective defects. For the stress phase the measurement window is defined by:
• The minimum stress time which can be consistently applied, which is given by the measurement equipment
• The maximum stress time applied
• The highest gate bias at which the oxide field does not cause oxide breakdown
• The lowest gate bias at which the defect under investigation has an occupancy close to one.
For the recovery phase, the measurement window is given by:
• The delay after stress at which the first point can be measured, which is given by the measurement equipment
• The maximum relaxation time applied
• The highest gate bias at which the defect still has an occupancy close to zero.
• The minimum voltage at which single recovery steps can be measured.
In general, applying the TDDS to extract the charge transitions times over wide ranges for stress and recovery bias is very time consuming. However, TDDS measurements can be performed in conjunction with RTN measurements, which allows to extract the capture and emission times of a defect over wide ranges of gate biases while also capturing both close to the intersection bias, as shown in Figure 4.12.
Parameter Extraction TDDS data are commonly processed using step detection algorithms, similar to RTN data. Compared to RTN data, defect parameter extraction is comparatively simple, as the emissions probabilities for the defects are not constant over the time of the experiment, but increase drastically after applying the recovery conditions. This allows to directly obtain the emission times from the relaxation phases. Defect parameter extraction for TDDS data will be discussed in Section 5.1.
The measurement methods discussed so far aimed at analyzing the behavior of the devices after a set amount of stress. In case the primary objective of characterization is the evolution of the device during stress, the OTF [97, 98] scheme may be used. For this, phases of stress are interrupted by short gate pulses to sample single points on the (), with the goal to cause minimal disruption of the applied stress. This is illustrated in Figure 4.13. Its main drawback as compared to the MSM method is that only a very small part of the () curve is sampled, which complicates interpretation of the results.
A measurement technique which can be used to learn about defects in devices of certain technologies is to record the hysteresis between voltage sweeps. For these devices, the gate voltage sweep during the recording of an () can subject them to a sufficient amount of stress to significantly alter its shape. In this case, MSM schemes may not be possible due to the failure to obtain a proper reference curve. To characterize these devices, repeated up- and down-sweeps can be recorded to obtain hysteresis curves as shown in Figure 4.14. These curves may be recorded at different sweep rates to obtain information about the numbers and time constants of the defects affecting the device. This method has been applied in the past to novel technologies for which a considerable amount of defects is still prevalent. For instance, devices based on graphene or SiC exhibit a significant hysteresis, while Si devices show almost no hysteresis behavior. Quite interestingly, while large area devices typically exhibit a continuous hysteresis behavior, single charge transition events become evident in voltage sweeps measured at nanoscale devices [70, BSJ6].