In this chapter results obtained using measurement, characterization, and simulation methods as discussed in the previous chapters will be presented. First, in Section 6.1, statistical analysis of single defect noise measurements on Si/SiOFETs will be discussed. Following this, in Section 6.2, characterization of BTI and RTN with the defect centric approach and performed on integrated Si/SiOpMOS arrays is shown. Finally, in Section 6.3, results of single defect characterizations on novel few-layer MoS channel devices are presented.
While the number of oxide defects affecting a MOSFET scales with the gate area, and thus decreases for smaller devices, the defects’ individual impact on the threshold voltage follows the opposite trend. In particular, the decreased channel area in scaled devices leads to a higher average impact of each defect on the device threshold voltage. This results in similar total threshold voltage shifts observed on small and large gate area devices. However, a significant difference between normal and scaled nodes is that the smaller number of defects leads to increased variability among nominally identical devices. This can affect the reliability of integrated circuits using scaled devices and requires statistical characterization of such devices to understand the reliability and variability of a technology and its characteristics under various operating conditions, i.e. biases and temperatures. For this, noise has been studied on more than 300 devices to extract statistical distributions of the defects’ impact on the threshold voltage, their location in the oxide, and their trap level.
The devices which have been used in this study are planar Si/SiOMOSFETs with a gate area of ≈0.15 µm^{2}. For the characterization of the devices a fully shielded Cascade/FormFactor PA300 semi-automatic wafer prober has been used. The electrical measurements have been performed using a dedicated custom designed defect probing instrument (DPI) [39]. The DPI has been equipped with three voltage sources, one for drain, gate, and bulk, and a low noise transimpedance amplifier stage in combination with a high-resolution voltage sampling unit for the source current. All connections have been made with double-shielded TRIAX cables to reduce spurious noise and ensure a high SNR.
To obtain statistics on the step height distribution, a fixed characterization sequence has been applied to each device tested. The sequence started with an initial () characterization, which has been used to verify proper operation of the DUT, to determine the gate voltages at which RTN is measured, and to map the recorded drain-source currents to an equivalent threshold voltage shift. The initial () measurements are shown in Figure 6.2 together with the bias range which has been used for recording the RTN signals.
After the initial () curve, the sequence continued with RTN traces recorded at the gate voltages corresponding to 20, 50, 100, 300, and 1000 nA at a drain bias of . At each gate voltage, five short RTN traces have been recorded with a sampling time of and a length of , followed by a longer trace with a sampling time of and a length of . The sequence has been chosen to characterize defects with a wide range of charge transition times. Figure 6.3 shows an example of a trace which has been recorded with .
For the statistics on defect location and trap level, the initial measurements with the fixed characterization sequence have been followed by additional RTN measurements on specific devices to characterize individual defects observed in the initial results in more detail. The measurement parameters for these recordings have been tailored to the individual defect to match their transition times and the gate bias range where they have been most active.
From the measured RTN data, the noise parameters of the defects producing the signals, i.e. the step heights and the capture/emission times of the discrete charge transitions, have been extracted. This has been done using the Canny edge detection algorithm, as outlined in Section 5.1.2. The Canny method could be chosen because there were only few active defects per device, and the SNR was sufficiently high. The significant advantage of this method is the high level of autonomy it provides. A long RTN trace analyzed with this method is shown in Figure 6.4.
To evaluate the impact of defects on the threshold voltage of the devices, the complementary cumulative density function (CCDF) of the step heights can be analyzed. The CCDF (or 1-CDF) which has been obtained from the measurements is shown in Figure 6.5. The distribution seems to be a bi-modal exponential distribution, with one set of defects exhibiting an average step height of 0.39 mV and a second set of defects showing an average step height of 1.09 mV. This observation is interesting, as for a simple gate stack with only a single oxide, i.e. without a second high-k material layer, only unimodal exponential distributions have been reported in literature so far, which would appear as a straight line in the plot.
To characterize the trap levels and vertical positions of the defects, more detailed measurements have been performed to extract the charge transitions times for a number of defects as shown in Figure 6.6.
This has been done for around 100 defects, and the estimation formulas given in Section 5.1.4 have been used to obtain the distribution of these parameters as shown in Figure 6.7.
The mean distance from the interface of the observed defects seems to be around 0.6 and their mean trap level lies 0.4 eV above the Fermi level at the interface, which is close to the Si conduction band at measurement conditions. It should be noted that the depth distribution of the probed defects does not represent the actual distribution of defects in the oxide, as only defects whose trap level is close to the Fermi level in the bias range chosen for the measurements can be characterized. As can be further seen in Figure 6.7, the estimation suggests some defects to be positioned outside the oxide. This is a consequence of the approximations made for this estimation. In particular:
• Gate/defect interaction is neglected. Defects interacting primarily with the gate thus may have inverted capture and emission time behavior which leads to negative distances.
• The prefactors in Equation (5.30) are assumed constant in the estimation, but do change with the channel carrier density, leading to overestimation of the distances.
• The estimation is only valid for two state defects, defects which can not be described using a two state model yield invalid results.
Also, charge transition times of defects have been measured whose intersection point is not visible within the measurement range. The extrapolation of the capture and emission times necessary in this case introduces additional uncertainty and may lead to some defects which have estimated positions close to the interface.
In Figure 6.8, the positions of the extracted defects are shown in a band diagram obtained from TCAD simulation. In addition, defect bands for electron and hole traps in SiOreported in literature [49] are shown for comparison. The peak of the energy extracted from the measurements is 0.1 to 0.2 eV lower than the literature values.
To get more accurate estimations for the trap depth and level, the charge transition times of the single defects have been simulated with Comphy [49]. By doing so, the trapping behavior of the single defects has been modeled using a two-state NMP model as outlined in Figure 3.4, together with a calibrated model for the device electrostatics. With this, the parameters for a subset of the defects have been obtained. The resulting distributions for trap level and distance to the interface are shown in Figure 6.9.
As can be seen, the peaks of the distributions for both the distance to the interface and the trap levels are slightly lower in the simulation results. The distribution of trap levels peaks at around 0.85 eV relative to Si midgap. The distribution which has been obtained from measurements on large devices in [49] is also shown in Figure 6.9. The mean energy which has been obtained in this work is lower than the one on large devices, which is at . The energy distribution is narrower and seems to coincide with the lower half of the energy distribution found for the large devices.
In conclusion, we have characterized defects in a Si/SiOtechnology and observed a bi-modal exponential distribution of step heights, which has not been reported so far for a device with a gate stack consisting of a single insulating layer, but is commonly observed on high-k devices [83, 140, 69]. The charge sheet approximation, as outlined in Section 3.2.2 gives values below 0.2 mV for this geometry, which—within the limits of this approximation—agrees with the first branch of the CCDF distribution measured. The origin of the second branch of the distribution indicating larger , however, remains open at this point and requires further investigation. For the trap depth and trap level distributions, the results obtained from the estimations show good agreement with the simulation results. Compared to the results given in [49], we have only observed defects in the lower half of the energy distribution. This may be due to limits of our measurement range, but it could also indicate that their distribution is broader than the actual distribution of trap levels.