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Advanced Electrical Characterization of Charge Trapping in MOS Transistors

4.2 Electrical Methods based on Defect Charge

Another way of characterizing defects in MOS structures is to measure the charge they emit or capture during (dis-)charging. This can be done for example by pulsing the gate bias, applying an AC voltage to the gate terminal, or in the case of TDRC by cooling the device, changing the bias, and then heating up the device. To obtain a sufficient response, these methods usually require larger devices than the methods based on channel conductivity, as well as a sufficient defect density.

Schematics for a measurement circuit as might be used for these measurements is shown in Figure 4.15. The gate bias at the DUT is supplied by a DAC and recorded using an ADC, often with separate wires from the DUT to mitigate parasitic effects introduced by the measurement lines. The bulk current is converted to an equivalent voltage using an OPAMP for trans-impedance conversion and is measured using a second ADC. The source and/or drain biases might be either supplied by a second DAC, shorted to ground or connected to bulk, depending on the measurement performed. Note that while a circuit as shown here allows a number of measurements to be performed, high-speed sampling is necessary and all processing has to be performed in software. If only a certain type of measurement is to be performed, parts of complexity might be shifted to the analog part of the circuit, e.g. signal mixing in the case of CV measurements and signal integration for CV, CP and DLTS measurements.


Figure 4.15: Schematics of a circuit as might be used for the charge based methods. With this setup, all signal processing has to be done in software. Particularly for CV measurements, part of the impedance extraction might be performed in hardware. In CP measurements, a hardware integrator might be used.

Measurement system used for this work

For the measurement methods as outlined in this section the same system as shown in the previous section (Section 4.1) has been used. Possible configuration for measurements of the gate and bulk current are shown in Figure 4.16. Note that with the configurations shown the current is never measured on a terminal where an AC signal is applied so as not to measure spurious currents resulting from stray capacitances.


Figure 4.16: Top: Schematic of the measurement system [39] employed in this work, equipped for the mea- surement methods presented in this section. Analog and digital subsystems colored in blue and orange, respectively; control signals omitted for clarity. As compared to Figure 4.3 for channel current measurements, an additional sampling unit included to measure the phase of the input signal for CV and DLTS measurements. Bottom: Possible configurations for gate and bulk current measurements. For CV measurements both the gate or the bulk current can be used to measure the MOS capacitance. Especially when testing devices on a wafer this decision may however influence the noise level of the measurement. Source and drain terminals—if available on the test structure—may either be shorted to bulk or supplied separately (as shown), in case the gate current is measured optionally with or without the AC signal. Depending on the chosen configuration the gate-source and gate-drain capacitances may be included in the measurement.

As compared to the previous section, a second sampling unit is shown here, which is used for CV and DLTS measurements to sample the phase of the AC part of the applied signal. To implement these measurements, the hardware and firmware of the units, which had originally been developed for channel current measurements, had to be modified. Most importantly, the sampling units have been redesigned to include a faster ADC, DC filters and (secondary) amplifiers, while the firmware of the voltage unit has been modified to allow for arbitrary signal output, and a synchronization clock line on the back-panel has been added to eliminate phase drift between the units due to the slightly different processor clocks. Additional functions have been implemented in the python software framework which allow to process the captured AC waveforms to extract the parallel capacitances and conductances either per voltage (for CV) or over time (for DLTS).

4.2.1 Capacitance-Voltage (CV)

In CV measurements, the small signal capacitance \( \intd {Q}/\intd {V} \) is recorded. It yields information on the device itself, as well as on defects contained. This can be achieved either by measuring the displacement current while sweeping the gate voltage (ramp method) or by superimposing a small AC signal on top of the DC gate bias and measuring the AC current (impedance method). The following discussion will focus on the impedance method, as it allows for greater flexibility in measurement parameters and further enables observation of the small signal conductance and extraction methods based on this.


Figure 4.17: Capacitance-voltage measurement. (a) DUT connected for measurement. (b) DUT in the various operation schemes with illustrated equivalent capacitance. In the depletion regime there are no free charges close to the interface. This can be interpreted as an increase in spacing between the plates of the equivalent capacitor. This in turn lowers the capacitance and gives the CV curve its characteristic shape. (c) Voltage and current signals during measurement. The phase and amplitudes of the voltage and current signals give the sought-after impedance. The offset voltage is swept in a staircase-like manner during the measurement. (d) Exemplary results of a CV measurement at multiple frequencies. The accumulation and inversion branches almost reach the oxide capacitance, while the capacitance in depletion is much lower. The inversion branch is generally steeper than the accumulation branch.


The principle of a CV measurement is illustrated in Figure 4.17. A small sinusoidal AC voltage—typically 50 mV at 100 kHz—is added to a DC bias which is slowly varied. This voltage is applied to the gate, while the bulk is forced to ground. Both, the gate voltage and the bulk current are measured simultaneously. Alternatively, the roles of gate and bulk may be switched, i.e. the voltage is applied to bulk and the gate current is measured. As stated before, this measurement can be performed either on MOSCAP structures or on MOSFET structures. The source and drain contacts are not necessarily required for the measurement. If they are available, they are usually shorted to ground or connected to bulk if the source and drain currents are to be recorded. The most fundamental difference of MOSCAP and MOSFET structures is that for MOSFETs the minorities required for inversion can be quickly supplied from the source and drain regions. This allows for faster gate bias sweeps compared to MOSCAP structures, where they have to be supplied by generation. The disadvantages of MOSFETs are the additional parasitics due to overlap of the source and drain areas with the gate. MOSCAP structures have the additional advantage of being effectively one-dimensional, allowing simple and accurate models to be used for description.

When CV measurements are performed, the gate bias is usually stepped from accumulation to inversion or vice versa to obtain the C-V and G-V curves, i.e. the small signal capacitance and conductance curves. The most important parameter for this measurement is the frequency of the applied AC signal, which may vary from kHz to GHz, but is usually limited to 1 MHz due to the significant increase in measurement effort beyond that point. The AC frequency determines how defects contribute to the measured CV curve as defects which can not follow the signal will not contribute to the measured capacitance. In MOSCAP structures, where minorities are not readily available from source or drain, the sweep rate in comparison to the minority response further determines the type of result obtained from the measurement.

Impedance Extraction

The small signal impedance \( Z \) is given by the division of the complex values of the AC gate voltage \( v\sub {G} \) and bulk current \( i\sub {B} \):

(4.7–4.9) \{begin}{`} Z &= \frac {v\sub {G}}{i\sub {B}} \\ |Z| &= \frac {|v\sub {G}|}{|i\sub {B}|} \\ \mathrm {arg}(Z) &= \mathrm {arg}(v\sub {G})-\mathrm {arg}(i\sub
{B}) \{end}{`}

The amplitudes and phase difference necessary for the calculation can be obtained from the sinusoidal signals either using analog circuitry or in the digital domain. In either case, a common approach to extract the phase shift is to employ I-Q demodulation as shown in Figure 4.18.


Figure 4.18: Extraction of the phase difference from a CV measurement. The current signal is mixed with the original voltage signal (left) and a phase-shifted signal (right). This gives signals with their sum and difference frequencies, i.e. \( 2\omega \sub {0} \) and \( 0\omega \sub {0} \). After low-pass filtering or integrating, the DC I and Q signals which are proportional to the imaginary and real parts of the current remain.

For this, the current signal is mixed with the voltage signal and successively low pass filtered or integrated to obtain an in-phase signal I which is proportional to the conductance—the real part of the admittance. By mixing the current signal to the \( \pi /2 \) phase-shifted voltage signal, the quadrature-phase signal Q is obtained, which is proportional to the susceptance—the imaginary part of the admittance. From these signals the relative phase shift can be calculated as \( \varphi = \tan ^{-1}(Q/I) \). Together with the measured amplitudes, the impedance of the device can then be calculated. It should be noted that commercial impedance analyzers or CV meters often give the impedance as values of an effective parallel or series R-C circuit, i.e.:

(4.10–4.11) \{begin}{`} Z &= R\sub {s} + \frac {1}{j\omega C\sub {s}}, &\text {for the series R-C circuit}\\ 1/Z &= 1/R\sub {p} + j\omega C\sub {p}, &\text {for the
parallel R-C circuit}. \{end}{`}

Since in general neither of these equivalent circuits will correctly represent the situation, it is preferable to obtain the complex impedance and then calculate the required quantities using the equivalent circuit most suitable for the combination of experimental setup, operating condition and device.

Defect Parameter Extraction

From the measured impedances, a variety of device parameters, including the oxide thickness, doping concentration, flat band and threshold voltage can be extracted. To find the contribution of the defects to a measurement, it has to be compared to some reference. There are several options on what to use as a reference.

One option is the high-low frequency method [100], where a low frequency measurement is compared to a high frequency measurement. The difficulty of this method comes from performing measurements at frequencies high enough for most defects to be inactive, which can require frequenices of up to 100 MHz. Another pitfall of this method can be additional effects unrelated to defects, which cause the high frequency curves to look different from low frequency curves. Another option is to measure at a single frequency and compare the measured curve to one obtained from simulation or calculation [101, 102]. While this seems easy from the measurement perspective, obtaining theoretical results which accurately represent the defect free device is difficult and requires exact knowledge of the device properties. Finally, measurements may be done at a single frequency in a MSM-like manner. The difference between subsequent measurements can then be linked to changes in the defect populations of the device. A more detailed discussion on how to obtain defect parameters from CV measurements can be found in the following chapter.

4.2.2 Charge Pumping (CP)

Charge pumping is a characterization technique first performed by Brugler and Jespers in 1969 [103] and later treated from a theoretical perspective by Groeseneken in 1984 [104]. The technique is most sensitive to fast defects located at or close to the interface. Unlike CV measurements, where defects are charged using a small sinusoidal AC voltage, CP uses a large rectangular AC voltage signal. The energetic distribution of defects can be probed by modifying the properties of the AC signal.


Figure 4.19: The CP technique. (a) DUT during measurement. During the high bias phase defects charge with minorities supplied from source and drain. In the following low bias phase, the minorities are emitted and recombine with majorities sourced from the bulk. Their amount is measured as the bulk current. (b) Gate voltage and bulk current during measurement. (c) Gate voltage parameters for the two measurement schemes. (d) Illustration of a measurement result.

For the measurement, the gate terminal of the MOSFET is connected to the signal source while the bulk is forced to ground and the resulting bulk current is measured or integrated. The source and drain terminals are shorted to ground or slightly reverse biased to allow injection of minority carriers during inversion. This is illustrated in Figure 4.19a. The gate of the device is then repeatedly pulsed between a high and a low voltage, (math image) and (math image) respectively, as shown in Figure 4.19b. The frequency used for CP measurements is commonly chosen in the 10 to 1000 kHz range, the steepness of the edges of the signal is critical to reproduce recorded measurements. During the high bias phase, the defects charge with minorities originating from the source/drain regions. In the following low bias phase, the defects then discharge and the released minorities recombine with majorities in the bulk, which have to be replenished from the bulk contact. These charges are measured as bulk current, and their amount depends on the number of defects which have been charged and discharged under the chosen measurement conditions.

To probe the energetic distribution of the defects, three basic measurement schemes are available. In the constant-amplitude scheme, the amplitude of the AC signal is held constant and its offset is sweeped, while in the constant-base-level scheme, (math image) is kept constant while (math image) is varied, as shown in Figure 4.19c. Likewise, in the constant-high-level scheme (math image) is kept constant while (math image) is sweeped. The total sweep range is commonly chosen from strong accumulation to inversion.

The resulting CP current looks as depicted in Figure 4.19d. The current depends directly on the interface trap density, the frequency, and the gate area. The defect densities can then be calculated from measurements with varying \( t\sub {r} \) and \( t\sub {f} \) using [104, 105]

(4.12) \{begin}{`} I\sub {cp} = 2 q k T f \overline {D\sub {it}} A\sub {G} \ln \left ( v\sub {th} n\sub {i}\, \sqrt {\sigma \sub {n} \sigma \sub {p}}\, \sqrt {t\sub {r}t\sub {f}}
\,\frac {|V\sub {fb}-V\sub {th}|}{|\vg [,h]-\vg [,l]|} \right ). \{end}{`}

Here, \( I\sub {cp} \) is the charge pumping current, \( A\sub {G} \) the gate area, \( \sigma \sub {n,p} \) the capture cross sections, \( n\sub {i} \) the intrinsic carrier concentration, and \( t\sub {r,f} \) the rise and fall times of the trapezoidal waveform.

4.2.3 Deep-Level Transient Spectroscopy (DLTS)

DLTS is a transient capacitance thermal scanning technique introduced by Lang in 1974 [106]. It was first used to characterize bulk defects in the depletion regions of p-n junctions. For this method, the device is biased negatively to form a depletion region below the junction. This bias is repeatedly interrupted by pulses of more positive bias, which cause non-equilibrium conditions in the device. After the bias has returned to its initial value, the defects charged during the pulse return to their equilibrium state. The transient change of the capacitance during this time is evaluated, in the original version using a double boxcar integrator, which measures the change in capacitance during a given time frame after the pulse. In addition, the temperature of the sample is slowly swept, and each defect band in the device will exhibit a maximum of the measured change in capacitance at a specific temperature, at which the time constants of the defects are in the range of the rate window, as shown in Figure 4.20 for one such peak.


Figure 4.20: Illustration of deep-level transient spectroscopy using rate windows. As the temperature of the sample is increased, the time constants of defects in the device decrease. Once the response time of a defect band coincides with the chosen rate window given by \( t\sub {1,2} \), the difference between the capacitance at these points—the DLTS signal—increases. At even higher temperatures the defects responses get too fast and the signal decreases again.

By changing the rate window, these temperatures slightly change. This allows to draw an Arrhenius plot for each peak and subsequent extraction of the corresponding defect energy. The method is able to distinguish between majority and minority carrier emission by choosing the level of the bias pulse in the reverse or forward regime.

With regard to MOS devices, interface trapped charge DLTS [107] was developed to characterize interface defects. In this variant, an accumulation pulse causes traps to be filled by majorities. After the pulse, the device is switched to deep depletion. This stimulates the traps to emit, which can be observed as a capacitance transient. While this is possible on MOSCAPs, the source/drain terminals on MOSFETs allow control of the minorities which extends the applicability of DLTS. With the source/drain diodes reverse biased, no minorities are injected from this regions which can interfere with the majorities. This allows characterization of the majority half of the band-gap. With the source/drain diodes forward biased, an inversion layer forms. This allows the characterization of the minority carriers in the other half of the band-gap.

A number of variants of DLTS have been developed over the years, including constant capacitance DLTS, lock-in amplifier DLTS, correlation DLTS, isothermal DLTS, computer-, Laplace-DLTS, and optical and scanning DLTS [105]. All the variants are targeted for the characterization of large structures, as a sufficient number of trapped defects are required to cause a recombination current of measurable size.

4.2.4 Direct-Current IV (DCIV)

DCIV is a relatively simple method to characterize the number of charged interface or near interface defects. The technique was first demonstrated by Neugroschel et al. [108]. For this measurement technique, the gate bias is swept from accumulation to inversion while the bulk current is recorded. At least one of the source/drain contacts has to be slightly forward biased to allow for minority carrier injection, as shown in Figure 4.21. During the sweep, minority carriers will be injected into the space charge region under the gate oxide. These minorities then combine at the interface with defect charges, causing majorities to drift towards the space charge region. To fulfill charge neutrality over the gate stack, charges have to be supplied by the bulk, which can be measured as a bulk current.

Note the dissimilarities between DCIV and CP. In CP, charges are not actively injected using source/drain biases as in DCIV but are made available by channel inversion. These minorities can then charge defects close to the interface, which are later emitted during accumulation to produce the CP current. In DCIV, the injected charges recombine with previously charged defects, causing the bulk current. Compared to CP, the gate bias range for DCIV is smaller.


Figure 4.21: DCIV measurement in the top emitter configuration. The drain and source diodes are slightly forward biased, causing minority injection into the space charge region. As the voltage is swept from accumulation to inversion, defect charges recombine with the injected minorities. This causes majorities to move towards the space charge region, in turn creating a measurable bulk current. The scale of this current depends on the number of defects discharging, as illustrated on the right.

4.2.5 Thermal Dielectric Relaxation Current (TDRC)

The last method presented here is the TDRC method. It was developed by Simmons and Mar in 1973 [109], is sensible to interface defects or near interface defects and can determine trap levels and lifetimes. The technique is based on the measurement of the non-steady-state generation or emission current over temperature. To measure the charge emission current of the defects, a MOSCAP is biased in accumulation and cooled to a cryogenic temperature. After cooling, the device is reverse biased, which leads to deep depletion as the thermal generation and recombination rates for carrier are negligible, which suppresses the formation of an inversion layer. Charge emission from the defects is negligible at this temperature. The device is then heated at a constant rate, which causes traps in the depletion region to emit, in turn causing a measurable emission current. Similarly, to measure the generation current, the device is first biased in inversion. After cooling, the reverse voltage is increased further, which again causes deep depletion. With the increasing temperature, additional carriers are generated, allowing measurement of the generation current. From the emission characteristics, the interface trap distribution in the upper (lower) half of the band gap can be determined for a n-type (p-type) semiconductor, while the generation current allows extraction of the carrier lifetimes.