5.3 Bias dependence of the recovery

In this section, the influence of the gate bias on the total shift is investigated. In particular, we expect that CP has a significant impact on the carrier exchange properties and therefore on the and oxide trap recovery since gate pulsing during CP corresponds to periodic Fermi level switches across the entire silicon bandgap. Standard recovery curves observed after NBTI stress of p- and n-channel MOSFETs are displayed in Fig. 5.3 (a). During recovery the gate-source bias was kept at a value close to the threshold voltage of the PMOS (-1.1), and NMOS (+1.1) device , respectively.

According to Fig. 5.3 (a), the first important finding is that both p- and n-channel devices recover in a comparable way (recovery rate NMOS = +2.0; recovery rate PMOS = +1.0), yet starting from completely different values visible immediately after the end of stress. Note that the shift of the NMOS device is negative within the first 200 post stress. Only after 200 the shift becomes positive indicating that the balance between negative and positive contributions to the shift has turned in favor of the negative charge.

In order to understand these results, a short CP measurement was appended right after the constant bias recovery period and changes in where converted into appropriate dependent shifts (). The conversion was performed according to Eq. 2.38 assuming a flat DOS and an amphoteric nature of interface traps. Recalling Subsection 2.1.3, the active interface state charge can be either positive or negative depending on the current Fermi level position during read-out. This implies that although the net charge build up after NBTI is positive in most reported cases (resulting in a negative threshold voltage shift after NBTI), individual contributions to the shift can interfere either constructively or destructively with respect to their present charge state. Hence, in a PMOS device biased at (-1.1) both interface traps and oxide traps are positively charged accumulating in a high negative threshold voltage shift. Conversely, in a NMOS device biased at (+1.1) oxide traps are positively charged while interface states are negatively charged, resulting in either a net positive or net negative threshold voltage shift depending on the dominating contribution.

In Fig. 5.3 (a), the -equivalent shifts for both devices are illustrated by full symbols. Clearly, after a long recovery period of 10,000, the remaining threshold voltage degradation is essentially due to interface states for the NMOS ( +8.0)), whereas for the PMOS the major part ( -2.5) of the visible shift must be attributed to positive oxide charge, only -5 being due to interface states.

In order to elaborate the role of interface states and gate pulsing on the recovery, we perform another key experiment using a second set of p- and n-channel devices, cf. Fig. 5.3 (b). On this second set we start immediately with CP after the end of stress, i.e. before recording the recovery curve at a constant gate bias. The CP periods were kept as short as possible ( 1) in order to prevent the previously discussed recovery induced by gate pulsing, cf. Fig. 5.2 (a). A comparison of the recovery characteristics illustrated in Fig. 5.3 (a) and Fig. 5.3 (b) shows that CP right after stress influences the subsequent shift considerably, consistent with [149, 151]. The levels of both NMOS and PMOS devices shift in the positive direction indicating a reduction in net positive charge. The recovery curve of the PMOS device even changes its direction after the CP measurement. When comparing the contributions of Fig. 5.3 (a) and Fig. 5.3 (b), one finds that they are nearly identical right after stress and after 10,000 recovery at constant gate bias. This again indicates that (at least for this particular wafer) interface state recovery is negligible provided the CP measurement cycles are kept short.