Besides the conventional static MSM and OTF techniques discussed in Section 3.1, recently similar methods including gate pulsing periods for charge pumping have been developed [63, 64]. During a CP MSM or on-the-fly interface trapping (OFIT) measurement, the gate junction is either pulsed continuously during stress and recovery or just occasionally for a short time when a CP measurement is performed. In the following, the first method, where the gate junction is pulsed continuously, will be indicated as pulsed CP MSM and pulsed OFIT while the latter method, where the gate junction is pulsed exclusively when measuring the CP current, will be denoted as interrupted CP MSM and interrupted OFIT. The gate biasing conditions applied during various kinds of CP MSM and OFIT are schematically depicted in Fig. 3.3. The stress-recovery intervals may follow a geometric progression in a similar way as discussed for the static MSM experiment.
Typically the base levels of the gate pulses ( ) are chosen identically during CP MSM and OFIT. The high levels of the gate pulses during OFIT () equal the former static stress voltage () subjecting the device periodically to electrical stress while measuring in parallel the CP current under stress conditions (). In [64] it was claimed that using the OFIT procedure the measurement is recovery free. The high levels of the gate pulse during CP MSM () correspond to a gate bias which exceeds in order to measure the maximum CP current but does not subject the device to stress during the measurement of . During the CP MSM procedure the device is assumed to recover.
During OFIT, the stress phase is periodically interrupted since the gate junction has to be pulsed toward accumulation in order to enable CP. The number of stress interruption events (accumulation phases) is considerably increased when performing pulsed OFIT as when applying interrupted OFIT. As a result, the total amount of degradation at the end of stress is decreased in comparison to an uninterrupted static stress experiment. To suppress recovery as efficiently as possible during OFIT, the duty cycle during pulsed stress may be extended from 50 to 99, thereby minimizing the time in accumulation where recovery may occur.
During CP MSM (Fig. 3.3 (a) and (d)) and during interrupted OFIT (Fig. 3.3 (c)) the effective stress time equals roughly the accumulated sum of the DC stress phases. During pulsed OFIT (Fig. 3.3 (b)), the effective stress time () is defined by the accumulated time intervals where the stress bias () is applied:
where is the pulse width, is the rise time and is the gate pulsing frequency. The effective stress time () yields approximately half of the actual stress time () when using a symmetrical pulse shape (duty cycle 50).
The degradation of the CP current during CP MSM () and OFIT () is typically calculated by subtracting the virgin CP current measured under CP MSM biasing conditions ():
Note that the degradation of the CP current is calculated for both and by referencing to the virgin CP current recorded under CP MSM biasing conditions (). This approach is considerably different from the one applied during static OTF where the stress induced increase of the drain current () is referenced to the first drain current value measured under stress conditions (). A mandatory requirement for referencing to when calculating is, to arrange the pulse shapes in a way so that the profiled energy ranges during CP MSM and OFIT coincide, cf. Eq. 3.10. This yields a better agreement but is still not completely correct since Eq. 2.35 does not consider the field dependence of different contributing defects. Eq. 2.35 implies a specific rule for aligning the pulse shapes in order to fix the gate pulsing slopes and hence :
In order to demonstrate the dynamics of interface state creation and recovery, the 1.5 high– PMOS device (HK2P/1.5/1) was stressed for an effective stress time of 100 at 125 °C using a stress voltage of -2.0 (oxide field approximately 6.6). Following the stress phase, a 100 lasting recovery phase was recorded. Four different experiments according to the four stress-relax modes discussed in Fig. 3.3 were performed on different devices having the same geometry. The results are summarized in Fig. 3.4: left hand side – linear scale; right hand side – logarithmic scale. During OFIT, the CP current was measured by pulsing the gate junction between +0.75 and -2.0, recording in parallel the CP current . During CP MSM, the gate bias was pulsed between +0.75 and -0.75, recording in parallel the CP current . During stress and recovery a symmetrical pulse shape was used with a duty cycle of 50, a gate pulsing frequency of 2 and rising/falling slopes of 20.
Device (a) was stressed in the ‘pulsed CP MSM’ mode, recording the CP current recovery during continuous gate pulsing following a 100 DC stress phase. After terminating stress, the first measured CP current value was recorded with a time delay of 40. Similar as observed for during static MSM (cf. Fig. 3.2 (b)), the CP recovery follows a dependence, yielding a CP relaxation rate () of -59.
Device (b) was stressed in the ‘pulsed OFIT’ mode, recording the CP current degradation during pulsed stress (effective stress time 100) and during the subsequent 100 pulsed recovery phase. Both, degradation and recovery, follow a power-law, however, with different exponents consistent with Fig. 3.2. The first measured CP current after initializing OFIT was recorded with an effective time delay of 40. As can be seen in Fig. 3.2 (b) (left hand side), the uncorrected OFIT data (open diamonds) shows a significant offset ( 71) at the very beginning and at the end of the stress phase. In fact, this initial increase accounts already for 40 of the total degradation (187) obtained at the end of the 100 lasting stress phase. Li et al. [64] attributed this initial offset to fast interface state creation at the very beginning of the degradation phase. Similarly, when switching from the pulsed OFIT mode to the pulsed CP MSM mode at the end of stress, a comparable decrease of 55 is obtained within the first 40 of recovery suggesting fast interface state repassivation as well when terminating stress. In order to check whether these initial offsets are actually caused by fast interface state degradation and recovery dynamics, as suggested by Li et al. in [64], we studied the OFIT and CP MSM technique in considerable detail [65]. Within this study we demostrated that the CP current is not stable once reaching the inversion regime, but keeps increasing slightly due to slow oxide traps increasingly contributing to the substrate current at elevated electric fields. Hence, data recorded during OFIT and CP MSM are not comparable in a straight-forward manner even when adjusting the rising/falling slopes in order to scan the same energy interval, cf. Eq. 3.10. By properly taking the contribution of oxide traps into account, we demonstrated [65] that no considerable fast degradation and recovery of interface states occurs at the very beginning and at the end of the stress phase revealing the major fraction of the obtained offsets between OFIT and CP MSM as a measurement artifact. After subtracting gate leakage currents and oxide trap contributions, we obtain a set of corrected OFIT data (open triangels) which displays considerably reduced offsets and different power-law dynamics: uncorrected data: = 0.12; corrected data: = 0.19. The relaxation rate associated with recovery during pulsed CP MSM () yields -11 which is considerably smaller than the one obtained in experiment (a) following DC stress. A further remarkable aspect of Fig. 3.4 may be found in the observation that the absolute amount of degradation obtained after NBTS is considerable larger when applying a constant stress bias (a) than when applying pulsed stress (OFIT), although both devices were stressed for the same effective stress time. In fact, the increase of the CP current measured 40 after terminating stress is 349 after constant bias stress but only 133 () after pulsed stress, indicating that interface state creation proceeds much more efficiently under DC bias conditions.
Device (c) was stressed in the ‘interrupted OFIT’ mode, recording the CP current by sporadically interrupting the constant bias stress phase at -2.0 by short (280) lasting OFIT pulses. Within these 280, three OFIT CP current values were recorded, the first one after 40, the following ones after a sampling interval of 100. During recovery, the CP currents were monitored by interrupting the constant bias recovery phase at -0.75 occasionally by short (280 lasting) CP MSM measurements (pulsing the gate junction between -0.75 and +0.75). Within these 280, three CP MSM CP current values were recorded, the first one after 40, the following ones after a sampling interval of 100. The interruption cycles during stress are performed in the OFIT mode, hence, they are supposed to be recovery free after [64]. Note that the overall degradation is much larger as opposed to the ‘pulsed OFIT’ mode yielding a similar CP current at the end of interrupted stress as obtained after DC stress in (a). During stress, we obtain the following power-law coefficients: uncorrected data: = 0.21; corrected data: = 0.27 consistent with many studies dealing with degradation dynamics of the interface [12, 8, 10]. The recovery rate () measured in the ‘interrupted CP MSM’ mode yields -30 which is again considerably smaller than the one obtained during ‘pulsed CP MSM’ in experiment (a) although the degradation level is similar at the end of stress. This indicates that interface state recovery proceeds more readily when pulsing the gate junction continuously during recovery.
Device (d) was stressed in the ‘interrupted CP MSM’ mode, recording the CP current as a function of the stress time by interrupting the constant bias stress phase at -2.0 by short (280) lasting CP MSM measurements. The procedure is similar as the one described in (c), however, this time the occasional measurements of the CP current during stress are performed in the CP MSM mode introducing possibly some additional recovery, since the gate junction is not pulsed toward the stress voltage during CP read-out. The subsequent recovery phase is performed identically as in (c) by interrupting the constant bias recovery phase at -0.75 sporadically by short (280 lasting) CP MSM cycles (pulsing the gate junction between -0.75 and +0.75). Although enhanced recovery might be involved as a consequence of an active stress interruption, the technique has considerable advantages over the OFIT method since it does not require any corrections on the CP current measured during the stress phase. The degradation and recovery dynamics are very similar as the ones obtained for the corrected data in experiment (c) ( = 0.25; = -) indicating that gate pulsing in the ‘CP MSM’ mode does not imply significantly more recovery than gate pulsing in the OFIT mode.
In order to check whether and how much recovery is involved in OFIT and/or CP MSM, we may analyze the evolution of the CP currents measured during the 280 stress interruption phases of the ‘interrupted OFIT’ and the ‘interrupted CP MSM’ experiment. The results are illustrated in Fig. 3.5.
Remarkably, both OFIT and CP MSM are affected with similar interface state recovery within the 280 lasting interruption phases of the constant bias stress challenging the proposal that the OFIT technique is actually recovery free. This statement holds at least for the used gate pulsing frequency of 2 and a duty cycle of 50. Applying this setup, the maximum time in accumulation where recovery may proceed during OFIT is only 250 within a single pulse periode. From this result we conclude that interface state relaxation is accelerated by gate pulsing toward accumulation. Note that the recovery rates () increase with the overall amount of degradation.
On the other hand, interface state relaxation is suppressed very efficiently when maintaining the gate bias constantly in inversion during recovery. To demonstrate this, we fade out the constant bias phases of the ‘interrupted CP MSM’ measurement and string together the CP currents measured during the 280 interruption phases. The results are illustrated in Fig. 3.6.
Following Fig. 3.6 (open diamonds), we obtain that CP current recovery proceeds efficiently only during the gate pulsing periods. Within the intermediate constant bias phases at -0.75, interface state relaxation is almost negligible. In particular, when ignoring the constant bias recovery phases in-between completely, one obtains similar recovery characteristics ( = -) as measured during pulsed CP MSM (cf. Fig. 3.4 (a); = -) where the gate is pulsed continuously (full diamonds) after stress. Hence, the overall recovery rate associated with interface state relaxation crucially depends on the way how the recovery cycle is performed. It is maximal when continuously pulsing the gate junction and becomes increasingly lower with increasing the ratio of the constant bias phases in-between. An exception to the rule is the ‘pulsed OFIT’ mode (cf. Fig. 3.4 (b)) where is small (-11) although the gate has been pulsed continuously during recovery. This may be explained by the lower overall degradation level at the end of ‘pulsed stress’ which may be affected already by a certain amount of recovery before switching to ‘pulsed CP MSM’ initiating the actual relaxation cycle.
In order to highlight the independence of the interface state dynamics on the oxide thickness and material, similar experiments have been performed on 30 SiO PMOS devices equipped with n gate poly (SM6P/30/H1). The HV device was stressed for an effective stress time of 100 at 125 °C using a stress voltage of -20.0 (oxide field approximately 6.3). Following the stress phase, a 100 recovery phase was recorded. The same four stress-relax modes discussed in Fig. 3.3 were performed on four HV devices (SM6P/30/H1), having, however, a different geometry (gate oxide area) as the previously discussed high– devices (HK2P/1.5/1). The results for the HV devices are illustrated in Fig. 3.7: left hand side – linear scale; right hand side – logarithmic scale. During OFIT, the CP current is measured by pulsing the gate junction between +2.0 and -20.0 recording in parallel the CP current . During CP MSM the gate bias was pulsed between +2.0 and -2.0 recording in parallel CP current . We have again used a symmetrical pulse shape with a duty cycle of 50, a gate pulsing frequency of 125 and rising/falling slopes of 20. Due to the much larger pulse amplitude during stress (22.0), a lower gate pulsing frequency had to be applied in order to adjust similar rising/falling slopes as applied to the high– device (HK2P/1.5/1) discussed previously.
By comparing the results of Fig. 3.7 to the results of Fig. 3.4, we obtain very good qualitative agreement indicating that oxide thickness and material do not play a significant role in NBTI degradation and recovery dynamics. Although the obtained power-law exponents of the SiO device (SM6P/30/H1) and the high– device (HK2P/1.5/1) differ slightly, the overall good correlation indicates that the basic physical mechanisms behind NBTI are essentially the same when comparing thin high– and thick SiO devices. The small discrepancies (larger power-law exponent and lower recovery rate for the thick oxide devices) may be attributed to the different pulsing frequencies used to characterize OFIT and CP MSM and naturally also to the fact that the tested wafers were fabricated in different factories having undergone a completely different process flow.
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