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8 Summary and Conclusions

Silicon device degradation and its correlation to hydrogen incorporation was investigated with a particular focus on the negative bias temperature instability (NBTI) which is typically observed when subjecting PMOS devices at elevated temperatures to a relatively large electric field across the gate oxide. As a consequence, a negative shift in the threshold voltage is usually observed causing a degradation of the drain current when measuring the same operating point again after stress.

Although the basic facts of the problem seem almost trivial at a first glance, an elaborated inspection of the electrostatics and dynamics of the effect quickly reveals that considerable precautions have to be taken for accurate extraction and correct interpretation of the phenomenon. For example, in the triode region of the device (\( |V_\mathrm {GS}| \geq |V_\mathrm {TH}| \)), the change in the drain current may be attributed to conventional defect charges counterbalancing the applied gate potential as well as to mobility degradation affecting the channel resistance as a consequence of Coulomb scattering at charged point defects. Different types of defects provide a broad distribution of energy levels located energetically close or within the silicon band edges. The trap states were found to be rechargeable which makes the gate bias (Fermi level position) during read-out an important parameter which crucially determines the detected amount of degradation. In the positive charge state the defect causes a negative contribution to the threshold voltage shift while in the neutral charge state the defect is electrically invisible and may undergo structural relaxation. The time constants for carrier exchange with the silicon substrate and for structural relaxation were found to be both bias and temperature dependent, suggesting a phonon assisted inelastic tunneling mechanism governing defect neutralization and a transition over a thermodynamic barrier for the subsequent relaxation event.

Due to the fact that the created damage starts to recover almost immediately after removal of stress, the delay time between the termination of stress and the actual measurement becomes an important parameter. In most reported cases (math image) recovery follows a log-like evolution in a semi-logarithmic time plot, suggesting a broad and homogeneous distribution of recovery time constants, and energy levels, respectively. Since the nature of the carrier exchange mechanism turned out to be inelastic, recovery is not only linked to the ‘time since end of stress’ but also to the characterization temperature. Indeed, defects recover more rapidly the larger the temperature. As a consequence, different analyzing temperatures complicate a direct comparison of measurement signals. Besides such dynamic inconsistencies, different analyzing temperatures affect the electrostatic magnitude of CP signals and transfer characteristics as well. This is because the scanned energy interval during CP and the Fermi level position as a function of the gate voltage depend on temperature. Thus, when characterizing degradation after stressing devices at different temperatures, a reasonable comparison of measurement signals is very challenging, if not impossible, as long as one is tied to the constraint of conventional measurement techniques that the stress temperature has to equal the recovery temperature.

This constraint was resolved in this study by the development and application of the ‘degradation quenching’ technique. By using in-situ polyheaters which surround the active silicon device and heat it up to a defined temperature when a power is applied, we are able to stress devices at different temperatures while characterizing them at a unique, much lower analyzing temperature. The degradation level remains conserved during the temperature switch by maintaining the stress bias until the lower characterization temperature has stabilized. This takes only a couple of seconds.

The application of the polyheater technique combined with bias ramp experiments like for example the ‘incremental sweep’ procedure has revealed several new characteristics of NBTI induced defects. It was found that there exists a specific defect type (probably an E\( \mathrm {’} \) center) which provides a large distribution of time constants. In particular, this defect is recoverable which means that it can be neutralized and annealed by moderate temperature enhancement or gate bias switches toward accumulation. Its energetic distribution with respect to the Fermi level position within the silicon substrate was investigated, showing two significant peaks, the first being located around midgap, the second being located in the upper half of the silicon bandgap. A second defect type was identified which is quasi-permanent. ‘Quasi-permanent’ means that the defect does not recover significantly due to single gate bias switches or moderate temperature enhancement and it appears also relatively stable in time within the scope of our experiments. However, even this quasi-permanent defect is not a 100\( \,\mathrm {\%} \) ‘permanent’ degradation. Long continuous gate pulsing at high frequencies or high temperature treatment (400 °C) let the defect recover almost completely. Nevertheless, in comparison to the previously described recoverable defect, the quasi-permanent defect appears often constant and shows completely different degradation and recovery dynamics. As opposed to the recoverable defect, the quasi-permanent defect correlates universally with the increase of the CP signal. This correlation was demonstrated for different temperatures and electric fields. The increase in the CP current is typically attributed to the creation of interface states. However, by converting the CP signal into an interface state dependent threshold voltage shift, it was found that only 30–50\( \,\mathrm {\%} \) of the quasi-permanent (math image) shift can be explained by fast SRH-like defects. According to our present microscopic model, the missing contribution is assigned to locked-in oxide defects which are assumed to be created when a hydrogen atom gets trapped into a recoverable E\( \mathrm {’} \) center, thereby blocking the relaxation of the formally recoverable oxide defect. The hydrogen atom is likely to come from broken Si–H bonds at the interface. Such a coupling of interface states and locked-in oxide defects would explain the observed universial correlation between the quasi-permanent (math image) shift and the CP current.

Besides the electrostatics and dynamics of individual defects, their correlation to hydrogen was investigated by means of BEOL process splits. In particular, it was found that the density of recoverable defects is practically independent of hydrogen, suggesting the precursor of (math image) to be an hydrogen-free oxygen vacancy. If this is the case, the E\( \mathrm {’} \) center is a reasonable candidate representing the recoverable defect. On the other hand, the quasi-permanent defects were found to strongly depend on the hydrogen budget within the gate oxide. The universal correlation between the quasi-permanent (math image) shift and the CP current has proven true also for different process splits. The strong link to hydrogen suggests a passivated dangling bond at the interface to be the precursor for quasi-permanent damage. The dynamic creation of quasi-permanent defects may be explained by the field- and temperature-assisted release of hydrogen from passivated Si–H bonds. Due to disorder induced variations in the bond properties, the Si–H binding energies are assumed to be dispersed symmetrically around a medium dissociation energy. As a consequence of this dispersion, different time constants for the release of hydrogen emerge. Based on the sum of defects properties collected within this PhD thesis, a microscopic model has been suggested which is capable to explain (at least qualitatively) the observed characteristics.

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