The following table contains information about the different hardware used in this PhD thesis.

Wafer ID	$t_\mathrm {OX}$	Oxide	Poly	Type	Process	Comment
SM5P/30/H1	30 $\,\mathrm {nm}$	SiO $_\mathrm {2}$	n $^\mathrm {++}$	PMOS	SNIT/PM	high H
SM5N/30/H1	30 $\,\mathrm {nm}$	SiO $_\mathrm {2}$	n $^\mathrm {++}$	NMOS	SNIT/PM	high H
SM5P/30/H2	30 $\,\mathrm {nm}$	SiO $_\mathrm {2}$	n $^\mathrm {++}$	PMOS	Standard	med H
SM5P/30/H3	30 $\,\mathrm {nm}$	SiO $_\mathrm {2}$	n $^\mathrm {++}$	PMOS	Metal 1	low H
SM6P/30/STD1	30 $\,\mathrm {nm}$	SiO $_\mathrm {2}$	n $^\mathrm {++}$	PMOS	Standard	med H
SM6P/30/STD2	30 $\,\mathrm {nm}$	SiO $_\mathrm {2}$	n $^\mathrm {++}$	PMOS	Standard	med H
SM6P/30/H1	30 $\,\mathrm {nm}$	SiO $_\mathrm {2}$	n $^\mathrm {++}$	PMOS	thin Ti/PM1	high H
SM6P/30/H2	30 $\,\mathrm {nm}$	SiO $_\mathrm {2}$	n $^\mathrm {++}$	PMOS	thin Ti/PM2	high H
SM6P/30/H3	30 $\,\mathrm {nm}$	SiO $_\mathrm {2}$	n $^\mathrm {++}$	PMOS	thick Ti/PM1	low H
HK2P/1.5/1	1.5 $\,\mathrm {nm}$	high– $\kappa$	p $^\mathrm {++}$	PMOS	imec wafer