1.3 Operating conditions causing bias temperature instability

When performing a bias temperature stress (BTS) on a MOS transistor, the device is usually heated to a defined stress temperature () and is then subjected to a relatively large electric field () across the gate oxide (GOX) by applying a defined stress bias to the gate junction of the transistor. In general, the degradation characteristics following BTS depend strongly on the polarity of the applied gate bias during stress and on the doping type of the device under test (DUT). When applying for instance a positive gate bias during stress, one speaks of positive bias temperature instability (PBTI) [7], while degradation following a negative bias stress gives the classical NBTI [8, 9, 10, 11, 12]. The largest amount of damage is usually observed when subjecting a p-channel metal oxide semiconductor (PMOS) transistor to negative bias temperature stress (NBTS).

During NBTI stress, all transistor contacts except for the gate are grounded resulting in a relatively homogeneous stress field, hence generating uniformly distributed defects along the entire gate oxide area. When neglecting small variations of the doping profile along the transistor channel, in particular close to the source/drain implantations, the dimension of the problem is reduced by the symmetry of the stress profile from three to one, perpendicular to the gate oxide-substrate interface. The band banding situation during NBTS is schematically depicted in Fig. 1.2 (a) for a PMOS transistor equipped with an n gate poly.

Due to the large negative gate voltage () applied during stress, the interface of the n gate junction () becomes heavily accumulated with majority electrons (). Hence, the Fermi level () remains pinned close to the conduction band edge at the polysilicon/silicon dioxide (SiO) interface, the band banding within the gate junction being approximately zero (0). On the other side of the gate oxide the moderately n-doped silicon substrate () becomes heavily inverted attracting injected minority holes () to the SiO/silicon (Si) interface. The depletion layer containing the bulk charge () approaches its maximum extension increasing the surface potential (), thereby bending the valence band edge at the SiO/Si interface toward the substrate Fermi level (). Following Fig. 1.2 (b), the band bending during stress (maximum surface potential ) may be estimated as

where is the intrinsic energy, is the valence band edge, is the elementary charge and is the bulk potential () which is given by

In Eq. 1.2, is the Boltzmann constant, is the donor doping density of the substrate material and is the intrinsic carrier concentration. When performing a full voltage loop along the band edges in Fig. 1.2 (a) one obtains

In Eq. 1.3, is the voltage drop across the gate oxide and is the flat band voltage which may be approximated as the difference in the work functions between the poly silicon gate junction and the silicon substrate assuming an ideal interface and no charges within the SiO gate oxide:

By inserting Eq. 1.4 in Eq. 1.3, one finds

From Eq. 1.5 a simple approximation for the electric field is obtained when stressing a PMOS transistor equipped with a n gate poly under NBTS:

1.1 being the silicon bandgap at a typical stress temperature of 125 °C. A similar deviation for a PMOS transistor equipped with a p gate poly yields the following approximation for the electric field during NBTS [13]:

where stands for the voltage drop within the gate poly junction (poly depletion) which is typically very small [14] due to the high poly doping density ( 0.1 for ).

When comparing Eq. 1.6 and Eq. 1.7, we come to the conclusion that a PMOS transistor equipped with a n gate poly has to be stressed under a larger gate voltage of approximately 1.0 compared to a PMOS transistor equipped with a p gate poly in order to generate similar electric fields during NBTI stress. The same considerations hold for an n-channel metal oxide semiconductor (NMOS) transistor as well, the holes at the SiO/Si interface being then supplied by the p-doped silicon substrate.

Typical stress fields applied during NBTI are between 2.5 and 8.0 [15]. The magnitude of degradation caused by fields below 2.5 is usually very small and hence often below the detection limit at typical stress temperatures (50 °C – 200 °C) within typical stress times (1 – 100,000). Fields above 8 introduce different degradation mechanisms like impact ionization by ‘hot’ carriers which tunnel through the gate oxide causing intrinsic TDDB due to the gradual formation of a conductive percolation path across the oxide [16, 17, 18]. When stressing thick oxide devices, the effect emerges earlier since the voltage drop across the gate oxide () is larger at the same .