The continued transistor scaling along Moore's law has encountered several bumps in the road once the scaling of planar devices was no longer physically feasible. The best candidate currently to replace FinFETs in future technology nodes is a stacked nanosheet gate-all-around transistor, which requires very complex fabrication steps, introducing significant process-induced variations. These variations have a critical impact on device performance and must be included when performing device and circuit simulations within a design technology co-optimization strategy, increasingly embraced by the semiconductor industry. Within PASTE-DCTO (Process-Aware Structure Emulation for Device-Technology Co-Optimization) we will investigate several strategies for variability-aware structure generation including process emulation and the development of process compact models. These models can be used to efficiently create a process-aware structure geometry without the need for the device designer to have expert knowledge of the fabrication steps being applied.

This project is financially supported by the Austrian Research Promotion Agency (FFG).