Cracks are observed in the passivation layers that cover IC chips in the areas where the top metalization layout geometry yields a three-dimensional profile for passivation deposition. To avoid such cracking and the subsequent device failure, it is essential to characterize the passivation deposition profile as a function of the layout geometry. This characterization can then be used to establish a set of layout design rules to mitigate crack formation. An easy and fast approach is the use of deposition simulation tools. Therefore, having a general purpose two- and three-dimensional topography simulator capable of handling different physical etching and deposition models is essential.
As our studies in two dimensions have shown, a void has significant influence on the timing delays and can substitute expensive low-k material in a controlled and reproducible manner. However, for the prediction of cracking effects, a two-dimensional void characteristic is not sufficient, rather its three-dimensional behavior must be considered. Therefore, three-dimensional void characteristics and their dependence on the metal profile have to be studied. The void characteristics and cracking effects depend strongly on different geometrical parameters of the layout. The parameter C, as shown in Figure 1, plays an important role in predicting cracking effects.
A set of three-dimensional investigations for different geometrical parameters has been and are being performed by ELSA (Enhanced Level Set Applications). How these geometrical parameters affect void characteristics, and subsequently C, is being studied. The goal of these three-dimensional investigations is to get a profile of the dependence of C on geometrical parameters that help process engineers choose the optimal geometrical parameters to avoid the cracks.