There is a wide range of areas in which high-voltage and power semiconductor devices can be applied. Driving loads directly from CMOS based logic circuits is used among others in automotive, mobile communication, and personal entertainment systems. To reduce costs, the combined integration of high-voltage and power devices together with CMOS low-power circuits on the same chip has recently become state-of-the-art. These devices are known as smart power devices and allow a reduction in the number of components that need to be assembled on circuit boards. Beside the cost reduction, the minimization of the number of components decreases potential errors.
Ensuring the reliable operation of power and high-voltage devices requires the consideration of impact ionization, temperature distributions, electric field distributions, surface influences, and interface degradations. Static and dynamic investigations must be performed likewise. The integration of low- and high-voltage devices on a single chip as is the case in smart power devices leads to additional parasitic effects which might cause break-down, latch-up, and snap-back behavior. The investigation of high-voltage devices by means of device simulation requires, in addition to profound physical models, a stable numerical system. In particular, the simulation of impact ionization often leads to poor convergence behavior due to its strong exponential dependence. Models used to estimate impact ionization in drift-diffusion based models depend not only on scalar values, but also on vector quantities. There are different approaches to how the vectors can be approximated. The influence of various vector discretization methods on the results of the simulations and on the convergence behavior have been investigated. Another numerical challenge arises from the fact that snap-back simulations need to trace non-bijective I/V curves, which makes curve-tracing algorithms necessary. Our work focuses on the simulation of reliability issues caused by impact ionization.