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# Emulation and Simulation of Microelectronic Fabrication Processes

#### B.2 DREAM Sequence Model

The closing of the top of the etched feature during the deposition cycles of the DREAM sequence can be avoided by properly tuning the ashing step. Otherwise, the closing leads to a decrease in etchant concentration reaching the bottom of the feature, leading to slowed etch rates. The step coverage $$n_r$$ of a deep via is given by [289]

$$n_r = \frac {2 e^{-h_T}}{1 + e^{-2h_T}} \quad , \label {eq::step_cov}$$

where $$h_T$$ is the Thiele modulus describing the conformality of a process. For $$h_T \ll 1$$, the process is conformal, while for $$h_T \gg 1$$ the concentration of active particles down the feature varies strongly. For simple geometries, analytical expressions for $$h_T$$ can be found, such as for a deep cylindrical via with diameter $$d$$:

$$h_T = \sqrt {3\beta } \, \frac {z}{d} \quad ,$$

where $$\beta$$ is the etchant sticking probability and $$z$$ the vertical coordinate down the via.

When $$h_T \approx 1$$, the process is transitioning between being conformal and non-conformal, meaning that tapering will start at this point down the via. The etchant concentration in Eq. (B.8) at this point down the via can be approximated as

$$n_r \approx \sech (1) \left ( 1 - \tanh (1) (h_T - 1) \right ) \quad , \label {eq::DREAM_approx}$$

where the etch rate in the via is directly proportional to this concentration. Therefore, for a given depth down the via $$z$$, the step coverage $$n_r$$ depends only on the top opening of the via $$d$$. Since $$n_r$$ and the etch rate ratio $$r_e$$ defined in the previous section are equivalent, they can simply be written as

$$r_e = n_r \propto -\frac {1}{d} \quad .$$

If there is no ashing, as is the case for the DREM sequence, the top diameter $$d$$ will decrease by a constant value for each cycle, leading to a linear decrease in $$d$$ with time. Assuming the ashing removes passivating material at a constant rate, the closing rate of the top opening is also slowed linearly. Therefore, the opening diameter $$d$$ at the top of the feature during the last cycle is directly proportional to the ash time $$t_a$$. If the ash time is increased, then also the final top opening diameter $$d$$ is increased if all other process parameters stay the same so that $$t_a \propto d$$. Therefore, this linear model for the effect of ash time on the etch rate ratio is written as

$$r_e(t_a) = p_0 - \frac {p_1}{p_2 + t_a} \quad ,$$

where $$p0$$, $$p1$$ and $$p2$$ are fitting parameters encompassing all physical parameters of the system. These also allow for a minimal ash time required to start removing passivating material, given as

$$t_0 = \frac {p_1}{p_0} - p_2 \quad ,$$

as well as a maximum time, above which additional ashing does not have an effect, written as

$$t_m = \frac {p_1}{p_0 - 1} - p_2 \quad .$$

Model Fitting

The above model was fit to experimental data in [268] for 100 cycles of the DREAM process. In order to give the best approximation of Eq. (B.8) using Eq. (B.10), the depth $$L_t$$ at which tapering is assumed to start in the model should be taken at the depth where $$r_e = 0.96$$, i.e. the depth at which the via diameter is 0.96 times the initial top opening diameter. From the experimental data, this depth was found to be $$L_t = \SI {24.96}{\micro \meter }$$ from the top opening of the via. Since the etch depth per cycle was found to be $$d_c = \SI {0.37}{\micro \meter }$$, the first 67 cycles were not influenced by the tapering. Measurements of the depths of vias for different ash times were taken to find values for $$D$$, which could be used to find experimental values of $$r_e$$ for each ash time $$t_a$$. These measured values and the model fit are shown in Fig. B.1 with error bars indicating the measured values and the least squares fit shown in orange. From this fit, the parameters for the model could be extracted and were found as $$p_0=1.17$$, $$p_1=\SI {0.59}{\second }$$ and $$p_2=\SI {-0.44}{\second }$$.

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### List of Publications

#### Journal Articles

• [1] X. Klemenschits, S. Selberherr, L. Filipovic, "Geometric advection and its application in the emulation of high aspect ratio structures", Computer Methods in Applied Mechanics and Engineering, vol. 386, 114196-1 – 114196-22, 2021, doi: 10.1016/j.cma.2021.114196.

• [2] A. Toifl, M. Quell, X. Klemenschits, P. Manstetten, A. Hössinger, S. Selberherr, J. Weinbub, "The level-set method for multi-material wet etching and non-planar selective epitaxy", IEEE Access, 8, 115406 – 115422, 2020, doi: 10.1109/ACCESS.2020.3004136.

• [3] X. Klemenschits, S. Selberherr, L. Filipovic, "Modeling of gate stack patterning for advanced technology nodes: A review" Micromachines, vol. 9, (invited), 631-10 – 631-31, 2018, doi: 10.3390/mi9120631.

#### Book Contributions

• [4] T. Reiter, X. Klemenschits, L. Filipovic, “Impact of high-aspect-ratio etching damage on selective epitaxial silicon growth in 3D NAND flash memory”, in Book of Abstracts for EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS). 2021-09-01–2021-09-03, pp. 54—57, 2021 (In press).

• [5] X. Klemenschits, S. Selberherr, L. Filipovic, "Modeling of gate stack patterning for advanced technology nodes: A review", in MDPI Miniaturized Transistors. (invited), 105 - 135, 2019, doi: 10.3390/books978-3-03921-011-4.

• [6] X. Klemenschits, S. Selberherr, L. Filipovic, "Unified feature scale model for etching in SF6 and Cl plasma chemistries", Book of Abstracts for EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS). 177 – 180, 2018, doi: 10.1109/ULIS.2018.8354763.

#### Conference Contributions

• [7] T. Reiter, X. Klemenschits, L. Filipovic, “Impact of high-aspect-ratio etching damage on selective epitaxial silicon growth in 3D NAND flash memory”, in Proc. EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS). 2021.09.01–2021.09.03, pp. 34–35, 2021 (In press).

• [8] L. Filipovic, X. Klemenschits, “Fast model for deposition in trenches using geometric advection”, in Proc. Simulation of Semiconductor Processes and Devices (SISPAD). 2021.09.27–2021.09.29, pp. 1–4, 2021 (In press).

• [9] X. Klemenschits, S. Selberherr, L. Filipovic, “Combined process simulation and emulation of an SRAM cell of the 5 nm technology node”, in Proc. Simulation of Semiconductor Processes and Devices (SISPAD). 2021.09.27–2021.09.29, pp. 1–4, 2021 (In press).

• [10] X. Klemenschits, S. Selberherr, L. Filipovic, "Geometric advection algorithm for process emulation", in Proc. Simulation of Semiconductor Processes and Devices (SISPAD). 2020.09.23–2020.10.06, pp.59–62, 2020, doi: 10.23919/SISPAD49475.2020.9241678.

• [11] X. Klemenschits, P. Manstetten, L. Filipovic, S. Selberherr, "Process simulation in the browser: Porting ViennaTS using WebAssembly", in Proc. Simulation of Semiconductor Processes and Devices (SISPAD). 2019-09-04 - 2019-09-06, pp. 339–342, 2019, doi: 10.1109/SISPAD.2019.8870374.

• [12] X. Klemenschits, S. Selberherr, L. Filipovic, "Fast Volume Evaluation on Sparse Level Sets", in Proc. International Workshop on Computational Nanotechnology (IWCN). pp. 113–114, 2019, ISBN: 978-3-9504738-0-3.

• [13] X. Klemenschits, S. Selberherr, L. Filipovic, "Unified feature scale model for etching in SF6 and Cl plasma chemistries", in Proc. EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS). 2018.03.19–2018.03.21, pp. 65–66, 2018, ISBN: 978-1-5386-4810-0.

### Curriculum Vitae

08/2017 – present

Doctoral Candidate and Research Assistant
Institute for Microelectronics, TU Wien
Vienna, Austria

09/2013 – 07/2017

Master’s degree, Physics with Nanoscale Physics
Thesis titled "Manipulation of the Dielectric Function of Silicon"
University of Birmingham
Birmingham, UK

09/2012 – present

Engineering Company Commander (Militia)
Austrian Armed Forces
Vienna, Austria