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Emulation and Simulation of
Microelectronic Fabrication Processes

2 Numerical Modelling

In this chapter, the computational methods required for the description of evolving material surfaces and interfaces are discussed.

First, the length scales involved in semiconductor manufacturing and the modelling approaches required and applied at these scales are discussed. Then, fundamental modelling approaches are reviewed and relevant assumptions about the modelled material surfaces and their interfaces are presented. This includes a description of continuum material descriptions and a motivation for their use in this work.

Different material representations for the continuum regime are introduced next, including a thorough review of the level set method which is applied for the modelling of material interfaces in this work. Different volume-based material representations are then presented, including a discussion of cell-based meshes in combination with the level set method.

Finally, different numerical approaches to the modelling of material evolution in time are presented. These include approaches developed within this work to overcome fundamental limitations of previous methods. The modelling of physical processes and their application to material evolution is ultimately provided.

2.1 Modelling of Reactor Regions

Modern silicon wafers are circular with a diameter of 300 mm or 3 · 10−1 m [22], while the smallest features generated in the manufacture are on the order of nanometres or 10−9 m [23]. Therefore, a full description of an entire wafer and all of its features would span more than \(8\) orders of magnitude, too much to be represented in a single simulation, as shown in Fig. 2.1. However, the simulation of a process can be divided into different size scales and performed separately, using the result of one simulation as an input for the next one. The largest part to be simulated is the space in which the wafer is being modified, the reactor. Therefore, the first step is to carry out a reactor-scale simulation to determine the properties of the gas-phase around the wafer, which includes the chemical composition as well as the electromagnetic properties which influence the fabrication processes.

(-tikz- diagram)

Figure 2.1: Length scales of semiconductor manufacturing. In the top left, a single SRAM cell of the 5 nm node with a total size of tens of nanometres is shown. It is part of the larger array of SRAM cells with a size of several micrometres shown in the top right. A large number of these arrays and additional control circuits form the SRAM region of the processor shown in the bottom right ©2021 IEEE [24]. One edge of the entire SRAM region is not larger than a few millimetres. The final chip is not larger than one centimetre, a small part of the wafer shown in the bottom left which is 300 millimetres in diameter ©2020 IEEE [25].

2.1.1 Reactor Scale Modelling

Every fabrication step of the semiconductor manufacturing process takes place inside a closed reaction chamber, such as a vacuum chamber or a plasma reactor. Gas inlets are used to control the flow of possibly several different reactive gases which ultimately control the composition of the atmosphere inside the reaction chamber. Using data from experiments [26] or simulations [27, 28], models for the distribution of different atoms or molecules in the gas phase above the wafer surface can be generated. Thus, engineers can optimise the reactor such that the molar concentration, as well as the angular and energetic distributions of gases impinging on the wafer surface are as uniform as possible across the wafer. This type of simulation does not model detailed features on the wafer surface, as they are too small to play a role in the description of the atmosphere above the wafer. However, the distributions generated by reactor scale models can be used as an input for subsequent feature scale simulations, which are then used to investigate how the specific properties of the reactor, such as gas inlet geometry and gas flow rates influence the feature scale topography and thus the devices fabricated on the wafer surface.

2.1.2 Feature Scale Modelling

The feature scale represents the scale at which electronic devices are built on the wafer. It is therefore closely tied to the size of the structure being manufactured and can range from a few nanometres for a single transistor [29] to several hundred micrometres for large microelectromechanical systems (MEMS) devices [30]. The different properties of the gas phase above the wafer, as discussed in Section 2.1.1, are used to model how different atoms or molecules impinge on the surface and subsequently react with it. Many different types of radicals can be involved in a single process, resulting in complex behaviour depending on the specific properties of the impinging species and the composition, as well as geometry, of the substrate. In plasma processes, energetic ions frequently hit the surface in a specific direction, heavily influencing chemical reactions and thus the effect of a process on the wafer. In order to model the impinging of atoms and molecules and the subsequent surface reactions properly, the materials in the feature scale must be represented robustly. Several different numerical methods for the representation of material interfaces will be discussed in the next section.