Continuous miniaturization of CMOS devices has allowed the extraordinary increase in performance of integrated circuits to become a magnificent reality. Numerous tough problems were solved on this exciting journey; however, growing technological challenges and soaring costs will gradually bring CMOS scaling to an end. This puts foreseeable limitations on future performance improvements, causing research on alternative technologies and computational principles to become paramount. The spin of an electron possesses several exciting properties suitable for future devices. It is characterized by two projections on a chosen axis – up or down, and it can change its orientation rapidly by utilizing an amazingly small amount of energy. Employing spin, as a compliment to electron charge, opens new exciting opportunities for developing conceptually new non-volatile nanoelectronic devices for future low power applications.
Silicon, the main material of microelectronics, is characterized by weak spin-orbit interaction and zero-spin nuclei, which gives rise to a long spin lifetime. This makes silicon perfectly suited for spin-driven applications. Spin propagation through an undoped 350μm thick silicon wafer supports the potential to fabricate silicon spin-based devices in the near future. However, the relatively large spin relaxation experimentally observed in electrically-gated lateral-channel silicon structures might become an obstacle in realizing spin driven devices, prompting an urgent need for a deeper understanding of the fundamental spin relaxation mechanisms in silicon.
We utilize a spin-dependent k·p Hamiltonian, where only the [001] valleys are included. Without strain the unprimed subbands are degenerate along the [100] and [010] directions. This degeneracy produces substantial mixing between the spin-up and spin-down states from the opposite valleys, resulting in hot spots characterized by strong spin relaxation (figure 1). In strained samples the hot spots are moved away from the center of the two-dimensional Brillouin zone (figure 2), which reduces their contribution to spin relaxation. Thus, strain used to enhance the on-current in nano-CMOS can also be used to boost spin lifetime.