Book Information

Miniaturized Transistors


  • Editor: Lado Filipovic and Tibor Grasser
  • Published: 2019. 202 pages.
  • ISBN: 978-3-03921-010-7 (Paperback); 978-3-03921-011-4 (PDF)

Complementary Metal Oxide Semiconductor (CMOS) devices and fabrication techniques have enabled tremendous technological advancements in a short period of time. In recent decades transistor scaling has enabled us to fit into our pockets what would be considered a supercomputer a few decades ago. However, as we approach the physical limits of scaling, the question frequently asked is: What is the future of CMOS? Sustaining increased transistor densities along the path of Moore’s Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of 10 years ago, technological advancements have accelerated to today’s FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes afterwards? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly simulate future devices.


Table of Contents:

  • Incorporation of Phosphorus Impurities in a Silicon Nanowire Transistor with a Diameter of 5 nm
  • High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor
  • Design and Characterization of Semi-Floating-Gate Synaptic Transistor
  • Process Variability—Technological Challenge and Design Issue for Nanoscale Devices
  • Empirical and Theoretical Modeling of Low-Frequency Noise Behavior of Ultrathin Silicon-on-Insulator MOSFETs Aiming at Low-Voltage and Low-Energy Regime
  • Remote Phonon Scattering in Two-Dimensional InSe FETs with High-κ Gate Stack
  • 3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance
  • Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET
  • Variability Predictions for the Next Technology Generations of n-type Six Ge1−x Nanowire MOSFETs
  • Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review
  • A Review for Compact Model of Thin-Film Transistors (TFTs)
  • The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?
  • Accelerating Flux Calculations Using Sparse Sampling