- 2.1 Definition of voltages and currents for two-terminal passive elements (a) and sources (b)
- 2.2 Simple circuit containing only conductances and current sources.
- 2.3 Currents and voltages for a device with
*N*-terminals as used by*MINIMOS-NT* - 2.4 Interaction of the coupled electrical and thermal circuits.
- 2.5 Electro-thermal compound model for a heat dissipating resistor
- 2.6 Voltages and currents for controlled sources.
- 2.7 Voltages and currents for a gyrator
- 2.8 Internal structure of the power monitor
- 3.1 Mobility vs. electric field in dependence of the basic parameters and .
- 3.2 Carrier temperature as a function of electric field for the approach of Hänsch as given by (3.44).
- 3.3 Carrier temperature as a function of electric field for the approach of Baccarani as given by (3.54).
- 3.4 Carrier mobility as a function of carrier temperature for the approach of Hänsch as given by (3.48)-(3.50).
- 3.5 Carrier diffusion coefficient as a function of carrier temperature for the approach of Hänsch.
- 3.6 Carrier energy relaxation time as a function of carrier temperature for the approach of Baccarani.
- 3.7 a) Carrier temperature response for a step in electric field when using the HD model. b) Carrier mobility and velocity response for a step in electric field when using the HD model.
- 3.8 a) Geometry of the homogeneous doped semiconductor. b) Geometry of Gummel's pentagon.
- 3.9 Influence of the boundary condition for the carrier temperatures on the distribution of the electric field inside the homogeneous p-resistor for various bias conditions. The horizontal lines belong to the special contact model (3.68).
- 3.10 Influence of the boundary condition for the carrier temperatures on the distribution of the hole temperature inside the homogeneous p-resistor for various bias conditions. The horizontal lines belong to the special contact model (3.68).
- 3.11 I-V curves for the homogeneously n- and p-doped resistors for DD and HD simulations. In addition, for the p-doped resistor the current for = 2 is shown.
- 3.12 Doping profiles of a) the long-channel and b) the short-channel NMOS transistor.
- 3.13 Electron concentration before the pinch-off point for the long-channel
NMOS for both transport models (
*x*= 2.12*m*). - 3.14 Electron concentration in the pinch-off point for the long-channel
NMOS for both transport models (
*x*= 2.12*m*). - 3.15 Comparison of the output characteristics of the long-channel NMOS for both transport models.
- 3.16 Comparison of the output characteristics of the short-channel NMOS for both transport models.
- 3.17 Comparison of the output characteristics of the long-channel PMOS for both transport models.
- 3.18 Comparison of the output characteristics of the short-channel PMOS for both transport models.
- 4.1 a) Original circuit and b) linearized companion model for the two-level Newton algorithm
- 4.2 Non-linear characteristic of the diode and the quantities for the linearized companion model
- 4.3 Comparison of the two different strategies: a) Device simulator as client. b) Device simulator as server
- 5.1 Splitting of interface points: Interface points as given in a) are split into two different points having the same geometrical coordinates b)
- 5.2 Effect of a separate potential variable on the initial-guess of the potential: a) with a separate potential variable the potential stays smooth inside the semiconductor region. b) directly applying the contact potential gives a large discontinuity of the potential.
- 5.3 Contact handling for mixed-mode
- 5.4 Lattice temperature distribution of a HBT with the isothermal contact model for different bias voltages.
- 5.5 Lattice temperature distribution of a HBT for different thermal contact conductances.
- 5.6 Heat generation distribution of a HBT for different thermal conductances.
- 5.7 Lattice temperature distribution of a HBT with the contact resistance model for different bias voltages.
- 6.1 Horizontal and vertical projection of the current solution for a diode.
- 6.2 Problematic constellation when using DBC.
- 6.3 Evolution of the node and contact voltages during iteration using DBC with no DC component. Until convergence 10 iterations are needed.
- 6.4 Evolution of the node and contact voltages during iteration using DBC with DC component. Until convergence 35 iterations are needed.
- 6.5 Evolution of the node and contact voltages during iteration using RBC with DC component. As for no DC component, 10 iterations are needed until convergence.
- 6.6 Effect of global and local damping on the solution variables: a) global damping b) local damping.
- 6.7 Placement of the iteration dependent conductance
*G*_{S}^{k}for one terminal. - 6.8 Simplified output stage of the A709 operational amplifier.
- 6.9 Evolution of the node voltages during DC operating point calculation for the OpAmp output stage with = 4.
- 6.10 Comparison of the iteration counters for a DC transfer characteristic for the OpAmp output stage with = 4.
- 6.11 Evolution of the node voltages during DC operating point calculation for the OpAmp output stage with constant shunt conductance.
- 6.12 CML inverter a) with simple current source b) and with current mirror.
- 6.13 Evolution of the node voltages during DC operating point calculation for the CML inverter with = 3.
- 6.14 Simulated DC transfer characteristic for the CML inverter.
- 6.15 CMOS inverter.
- 6.16 Evolution of the node voltages during DC operating point calculation for the CMOS inverter with = 1.
- 6.17 Simulated DC transfer characteristic for the CMOS inverter.
- 7.1 Geometry of the HBT.
- 7.2 Net doping profile of the HBT.
- 7.3 Electric field inside the HBT in dependence on the collector-emitter voltage for both DD and HD simulation.
- 7.4 Electron velocity inside the HBT in dependence on the collector-emitter voltage.
- 7.5 Electron temperature inside the HBT in dependence on the collector-emitter voltage.
- 7.6 Contact temperature of the HBT in dependence on the base-emitter voltage.
- 7.7 Collector and base current of the HBT in dependence on the base-emitter voltage. For the self-heating model the collector current is approximately independent of the thermal contact conductance.
- 7.8 Comparison of the current gain of the HBT for self-heating with different thermal contact conductances and the model without self-heating.
- 7.9 Comparison of the current gain of the HBT for self-heating with different contact
temperatures and
*T*_{L}= 300*K*. - 7.10 Fictitious transient step response of the HBT when turning self-heating on.
- 7.11 Five-stage CMOS ring oscillator
- 7.12 Node voltages of the long-channel five-stage CMOS ring oscillator. DD and HD match perfectly.
- 7.13 Node voltages and of the short-channel five-stage CMOS ring oscillator for DD and HD.
- 7.14 Five-stage CML ring oscillator
- 7.15 Open-loop DC transfer characteristic for the CML ring oscillator.
- 7.16 Open-loop gain for the CML ring oscillator at the last three stages.
- 7.17 Oscillation of node voltage of the five-stage CML ring oscillator. Large discrepancies between DD and HD are observed.
- 7.18 Oscillation of the collector current of
*T*_{1}of the five-stage CML ring oscillator. Current levels are approximately the same for both transport models. - 7.19 Schematic of a differential pair
- 7.20 Thermal equivalent circuit for the differential pair
- 7.21 DC transfer characteristic of the emitter-coupled pair for different thermal models.
- 7.22 Contact temperatures of the transistors
*T*_{1}and*T*_{2}against the input voltage. - 7.23 Contact temperatures of the transistors
*T*_{3}and*T*_{4}against the input voltage. - 7.24 Transient response of the emitter-coupled pair for different thermal models.
- 7.26 a) Simple layout demonstrating mismatch due to improper placement of the input stage and b) improved placement of the input stage on thermal isolines.
- 7.27 Schematic of the A709 OpAmp.
- 7.28 Thermal equivalent circuit used to simulate thermal interaction for the A709 OpAmp.
- 7.29 DC transfer characteristic of the A709 for constant lattice temperature and considering thermal coupling of the input and output stage.
- 7.30 Open-loop gain of the A709 for constant lattice temperature and considering thermal coupling of the input and output stage.
- 7.33 Temperature difference of the input transistors
*T*_{1}and*T*_{2}during the DC transfer characteristic. - 7.34 Dissipated power
*P*_{d}in the output stage during the DC transfer characteristic. - A.1 a) Geometry and b) temperature distribution of a material block.
- A.2 a) Grid point
*i*and 4 neighbors used for the discretization of the lattice heat flow equation. b) Electrical analog circuit for the lattice heat flow equation. - A.3 Electrical and thermal modeling of several transistors.
- B.1 Class hierarchy within the
*Algorithm Library*and definition of the communication interface to the simulator.

1999-05-31