The goal of the proposed research is the evaluation of an entirely new path to fabricate strained Si nano-devices that are compatible to Si CMOS processing. The idea is to fabricate field effect transistors from strained Si bridges, which have been manufactured by disposing embedded, sacrificial Ge islands (dots). To achieve the required positioning of the Ge dots, templated self-assembling will be explored. This approach promises high speed electronics, due to the large mobility of carriers in strained Si, substantially reduced short channel effects, since the thickness of the channel is defined by an air bridge, and an improved thermal conductivity, which is attributed to the all Si device design.
Alternative paths for the templated self assembly of Ge dots will be investigated, including e-beam lithography and x-ray interference lithography for the pre-pattern and molecular beam epitaxy as well as chemical vapour deposition for the growth of the ordered Ge islands. Care will be taken to analyse by grazing incidence x-ray diffractometry the strain and its uniformity in the Si bridges before and after removal of the Ge dots as well as after the fabrication of the gate stack.
The actual devices will be processed using CMOS compatible Si device technology. The fabrication of the devices will be accompanied by intensive structural and electronic modelling. Special emphasis will be put on the strain distribution in the Si channel prior and after the removal of the dots and its impact on the electronic properties of the devices.
To tackle these complex multi-faceted project, experts in the field of crystal growth, structural and electronic analysis, device processing, modelling of crystal growth and device simulation will closely cooperate. As a result detailed insights into the correlation between structural and electronic properties in Si nano-electronic devices are expected as well as the successful fabrication of this new device - the D-(isposable)Dot_FET.