Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs
The quality of the interface between semiconductor and insulator material has always played a major role for the functionality of a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET). This also applies to silicon carbide (SiC) MOSFETs which show superior properties when used as switches in power conversion applications. However, electrically active defects on an atomic scale located near the SiC/SiO2 interface determine the stability of the device parameters and increase its on-state losses due to a perturbation of the electrostatics upon being charged. The kinetics of these charge transfer processes are strongly influenced by the applied bias and surrounding temperature, hence summarized under the term Bias Temperature Instability (BTI). While the total defect density at the interface has been significantly reduced, by e.g., the introduction of nitrogen-containing post-oxidation anneals, which led to improved channel carrier mobility and stability of the threshold voltage, the exact nature of these defects is still unknown. Another detrimental effect caused by oxide defects are enhanced gate leakage currents, which are enabled by the traps acting as charge transition centers, termed Trap-Assisted Tunneling (TAT) currents. Since both effects are widely accepted to be caused by inelastic tunneling processes, the underlying charge transfer reactions can be described by the Non-Radiative Multi-Phonon (NMP) model. While the application of this model has revealed many details of the charge transfer kinetics and led to the identification of a few potential defect structures in Si MOSFETs, its application to SiC MOSFETs has not been successfully demonstrated. One reason for this is the large defect density, which hampers defect parameter extraction by conventional methods. Therefore, a novel Effective Single Defect Decomposition (ESiD) algorithm is applied in combination with the reliability simulation framework Comphy to simulate the measured transient threshold voltage shifts caused by charge transfer at a large ensemble of defects, which is characterized in various lateral channel MOSFETs. The obtained defect parameters are then compared for their consistency over several SiC technologies and with those reported from ab-initio calculations for suspected defect structures. Additionally, a new two-state NMP based TAT modeling approach is presented in this work, including charge hopping between defects. This novel model is then applied to successfully explain TAT currents obtained in SiC/SiO2 MOSCAPs. Further verification of the model with widely studied TAT currents measured employing capacitors based on ZrO2 allows to draw conclusions about the nature of these charge transition centers in both binary oxides. A defect parameter comparison to those obtained from DFT calculations of models from a defect class, so called polarons, results in excellent agreement, rendering polarons a likely defect candidate responsible for TAT. Finally, features of both reliability threats, BTI and TAT, are reasonably well explained by two-state NMP charge transfer kinetics in SiC-based MOSFETs. The extracted defect parameters suggest a few structural defects as the root-cause of reliability issues in SiC MOSFETs due to their consistency with ab-initio based parameter extraction.