Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs

4.7 The Multi-TAT Regime

A multi-TAT current or charge hopping current with charge transitions involving numerous defects, has been suggested to contribute to gate leakage currents in a number of previous works [122, 240, 106, 219]. However, multiple mechanisms can lead to leakage currents, and the importance of multi-TAT has not been quantified in terms of its contribution to these total leakage currents. In this section, by using the physical model for calculating charge hopping currents as described in the previous sections, a quantification of the multi-TAT conduction shall be given. Thus, in order to analyze the requirements of a material stack employing a defective dielectric layer for multi-TAT to significantly contribute to a total leakage current density, it is necessary to analyze the average number of defects $\langle N \rangle$ which act as charge transition centers. Therefore, $\langle N \rangle$ is defined as

$(4.67) \{begin}{align} \langle N \rangle = \frac {\sum _{i} I_{i,\mathrm {min}} N_i}{\sum _{i} I_{i,\mathrm {min}}} \label {equ:n_ave} \{end}{align}$

with $I_{i,\mathrm {min}}$ being the minimum current between two defects or reservoir and defect and $N_i$ denoting the number of defects within the path $i$ . The summation is carried out over all possible percolation paths and divided by the total current.

$ \mathcal {O}\left ( \vert N \vert \mathrm {log} \vert N \vert + \vert E \vert \right ) $

For that, all individual percolation paths $i$ and their contribution $I_i$ to the total current need to be identified. In order to efficiently identify the path with the largest, second largest and so on contribution path finding algorithms, as mainly used for instance in navigation systems, provide a perfect solution. Therefore, the single-source shortest-path algorithm of Dijkstra [242] is used in an adapted way to calculate all percolation paths and the number of contributing defects in each. Hence, after calculating the charge transitions between all defects and the reservoirs for a certain (V_G, $t$ , $T$ ) as described in Section 4.3 in a post- processing step, a graph connecting all the defects is created to execute the algorithm. Each defect represents a node of the graph, with the channel representing the starting and the gate the end node. Since a shortest path algorithm is used, a distance metric on this defect connection graph needs to be introduced. As the search should identify the dominant current paths, the Markov transition probabilities are used as the metric on the graph. Thus, the edges between the nodes representing the current that is conducted in between the defects are weighed by the inverse of the multi-TAT terms of (4.56), i.e. Markov transition probabilities. In the same way the edges that connect the nodes with the starting node are weighed by the inverse of the charge trapping term and the ones connected to the gate by the TAT current term.

The algorithm is shown in the flow diagram in Figure 4.11 and first initializes two lists $\mathcal {D}$ and $\mathcal {P}$ that are required in the standard form of the algorithm to store the distances of the start node to the actual node. Within $\mathcal {D}$ , the shortest path is stored and $\mathcal {P}$ represents a list with the preceding nodes in that path. The Dijkstra algorithm is then started by setting the distance to the start node at $n_s$ to $d_s = 0$ . For increasing the performance to $\mathcal {O}\left ( \vert N \vert \mathrm {log} \vert N \vert + \vert E \vert \right )$ [241], with $N$ nodes and $E$ edges, a Fibonacci heap $\mathcal {H}$ is used with the keys of the nodes $n_i$ being the distances $d_i$ from the starting node.

The priority list is then reduced in each iteration by removing the node $n_i$ with the smallest distance, and updating all adjacent node distances and setting their predecessors to $n_i$ . In the next step, the heap is updated with the new distances and $n_i$ is removed. From the final list of predecessors of the end node $n_\mathrm {e}$ , the shortest path is read with the number of nodes being the defects in the percolation path. For the purpose of extracting all percolation paths, the edge with the smallest weight, i.e. smallest current $I_{i,\mathrm {min}}$ , is then removed from the initial graph and the number of nodes is weighed by this current. This ensures charge conservation, as can be easily seen from Kirchhoff’s law within the network, i.e. missing current contributions or double counting are ruled out. The procedure is then repeated until no path can be found from $n_\mathrm {s}$ to $n_\mathrm {e}$ . With all paths $i$ analyzed for the contributing defects $N_i$ percolating the minimum current $I_\mathrm {min}$ within the path the average defect number as a measure of multi-TAT relevance can be calculated by (4.67).

Applying this algorithm to the example shown in Figure 4.12, one ends up with four conducting paths (removing the minimum edge of each dominant path ensures charge conservation, i.e. no double counting of currents) sorted by the order of their extraction:

• Channel - 1 - Gate with $I_\mathrm {min} = \frac {1}{4} I_\mathrm {tot}$
• Channel - 1 - 3 - Gate with $I_\mathrm {min} = \frac {1}{3} I_\mathrm {tot}$
• Channel - 1 - 2 - Gate with $I_\mathrm {min} = \frac {1}{4} I_\mathrm {tot}$
• Channel - 1 - 2 - 3 - Gate with $I_\mathrm {min} = \frac {1}{6} I_\mathrm {tot}$

This example shows, that the algorithm does not necessarily find the path conducting the largest fraction of the total current, as the weighing of edges is conducted by the Markov transition probability instead of the resistivity. However, the exact ordering of the paths is irrelevant for the computation of the average defect number, which for the example by employing (4.67) reads:

$(4.68) \{begin}{align} \langle N \rangle = \frac {1}{4} \times 1 + \frac {1}{3} \times 2 + \frac {1}{4} \times 2 + \frac {1}{6} \times 3 \approx 2.33 . \{end}{align}$

With the percolation path analysis at hand, the properties of a gate stack and the defects within the insulator that lead to a relevant multi-TAT current shall be discussed. Therefore, a poly-Si/SiO₂/Si gate stack is employed with a single defect band. Three oxide thicknesses with 5 nm, 10 nm and 20 nm, with the defect band located at ET = 0.95 eV with respect to the Si mid-gap are investigated. This specific selection of the energetic position of ET allows for electrons being captured from the channel at small to medium oxide field strengths due to its small relative distance to the Si conduction band and reduces the probability of the electron to be directly emitted to the oxide conduction band due to the relatively centered position within the SiO₂ band-gap. A constant number of defects $\overline {N}$ = 50/nm is introduced in the oxide layer, resulting in 250, 500 and 1000 defects used within each simulation, respectively. As the relative distance of the effective defect levels between individual defects is determined by ET and its distribution, the most relevant parameters for enabling multi-TAT transitions are given by ER and the distance between the defects, i.e. the defect density. In order to study their impact, these parameters are varied from ER = 0.3 eV to 1.5 eV and NT = 1 × 10¹⁸/cm³ to 1 × 10²⁰/cm³. Note that the relaxation energy refers to the defect/reservoir transition and the transformed ER for defect/defect transitions is approximately a factor of two higher, see Section 4.4.1. The NMP parameters and ranges of this fictive defect band are summarized in Table 4.1.

$ \left \langle E_\mathrm {T} \right \rangle $

For all three gate stacks, bias sweeps from V_G = 0 V to $V_\mathrm {G,max}$ = 5 V, 10 V and 20 V were applied in the simulation, resulting in comparable oxide field strengths at $T$ = 300 K. The steady-state TAT currents were then analyzed with the modified Dijkstra algorithm as discussed above. Figure 4.13 shows the resulting average number of defects $\langle N \rangle$ for the three oxide thicknesses together with the associated steady-state current densities at intermediate field strength of $E_\mathrm {ox} \approx$ 4 MV/cm. The black colored $\langle N \rangle$ indicate the parameter tuples (ER ,NT ) resulting in significant leakage current densities above a low power limit of 1 × 10⁻² A/cm² for logic devices [243], while the green numbers indicate current densities between 1 × 10⁻⁶ A/cm² to 1 × 10⁻² A/cm² which can be considered moderate leakage currents in RAM applications while the red fields with current densities below 1 × 10⁻⁶ A/cm² are not considered to contribute to a relevant leakage current. Thus, it can be seen that only the thinnest oxide exhibits relevant multi-TAT currents for the logic current limit at realistic bulk defect parameters (ER $>$ 0.9 eV, NT $<$ 1 × 10²⁰/cm³). Multi-TAT leakage current densities relevant for logic applications are only observed for medium densities NT $\geq$ 1 × 10¹⁹/cm³ for the 10 nm oxide, with more defects in the leakage paths on average. In the thickest oxide multi-TAT leakage can be considered relevant only for the highest densities at low ER , thereby resulting in hopping over more than 10 traps.

A detailed spatial resolution of the multi-TAT percolation paths in the different gate stacks is provided in the band diagrams in Figure 4.14 at ER = 0.9 eV and NT = 1 × 10¹⁹/cm³ (central field in Figure 4.13).

Band	$\left \langle E_\mathrm {T} \right \rangle$	$\sigma _{E_\mathrm {T}}$	$\left \langle E_\mathrm {R} \right \rangle$	$\sigma _{E_\mathrm {R}}$	$x_\mathrm {T,max}$	NT
multi-TAT	0.95 eV	0.1 eV	0.3 eV to 1.5 eV	0.1 eV	-	10¹⁸/cm³ to 10²⁰/cm³

Modeling of Defect Related Reliability Phenomena in SiC Power-MOSFETs

4.7 The Multi-TAT Regime

Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs