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Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs

2.2 Peculiarities of SiC MOSFET Characterization

As discussed in Chapter 1, a large number of electrically active defects in the vicinity of the conducting channel typically implies, among other detriments, instabilities of the device characteristics. Defect densities of approximately two orders of magnitude higher as compared to Si-based devices [20] bring along many challenges for the characterization of device parameters and the extraction techniques developed for Si-based MOSFETs, e.g. distorted CV-measurements for the extraction of the surface potential or additional readout delays in MSM sequences. As these techniques are impaired by alterations due to the continuous charging and discharging of the defects, a few considerations need to be taken into account, in order to make extracted quantities (like Vth) comparable (partly noted in  [90]):

  • • As the application of any small external bias to the device terminals will alter its pristine characteristics, the full device history should be noted and taken into account for the extraction of ∆Vth.

  • • The pristine device state should be recorded as fast as possible using the narrowest bias range required, to minimize changes to the device during the initial characterization, a step that generally serves as the reference for further analysis.

  • • Measurement delays for recording ∆Vth need to be kept as short as possible. To extract operation relevant shifts of Vth at AC gate signals in the kHz regime, the measurement delay needs to be kept in the µs regime. For the extraction of faster degradation components at room and operation relevant temperatures (elevated due to self-heating), additional extraction at low temperature needs to be conducted. This is possible due to the strong temperature dependence of the defects time constants [161].

In order to make the extraction and degradation of Vth from measurement data more comparable among different SiC MOSFETs, Rescher et. al proposed a so called pre-conditioning scheme [87, 88]. Within this scheme a defined gate bias pulse in the MOSFETs accumulation regime is applied after the device is stressed and before Vth is read out. This pulse at typically negative biases (for a nMOS transistor) leads to accelerated emission of electrons that had been are captured during a pBTI stress phase. Most of the defects that are responsible for short term degradation emit previously captured electrons, and only a more permanent part of Vth degradation remains. Consequently, only defects with significantly larger charge emission time constants remain charged before Vth read out. While this scheme has the advantage of a more “stable" Vth read out, as the Vth value extracted is less dependent on the exact read out time after the stress phase, a large fraction of Vth instability is not captured by the scheme. This bears the advantage of making extracted absolute Vth values more comparable between different technologies and within industry standard stress tests, in which many devices are stressed in parallel and readout subsequently at varying read out times. On the other hand, if the scheme is used to reproduce charge trapping kinetics in simulations, the charge transfer kinetics need to reproduce also the pre-conditioning scheme, instead of using the measured (math image) directly for the PBTI simulation, e.g.  [162].

In the work of Feil et. al [CSJ10], the impact of a gate voltage pulse on the extraction of device parameters has been investigated in detail for different commercially available SiC MOSFETs. The time dependence of the readout of absolute parameter values like Vth, \( R_\mathrm {on} \) or \( g_\mathrm {m} \) is quantified with typical errors of more than 10 % for common measurement readout delays and the dependence on pulse length and pulse bias is discussed. It is also shown that the pre-conditioning method can be advantageous to characterize long-term instabilities of Vth, i.e. classical BTI. However, it does require a careful calibration of the pulse length and width to remove the fully reversible fast recovering part of both electron and hole trapping that is inevitable in the scheme. For each technology investigated, the ideal readout close to charge trapping equilibrium can be calibrated to lie within the first milliseconds of the readout [CSJ10].

In this work the effect of a depletion or accumulation bias pulse on defects with slow and fast capture and emission times is reproduced by a transient simulation in Section 5, thereby capturing the pre-conditioning charge transfer kinetics. The full transient simulation of the whole stress and measurement scheme, including initial (math image)( (math image)) curves, is therefore the rigorous approach to cover the widespread charge transfer kinetics within SiC based MOSFETs in a physical simulation.